diff --git a/src/db/db/dbDeviceClass.cc b/src/db/db/dbDeviceClass.cc index 7ff6619f3..d16daf212 100644 --- a/src/db/db/dbDeviceClass.cc +++ b/src/db/db/dbDeviceClass.cc @@ -136,13 +136,13 @@ bool AllDeviceParametersAreEqual::equal (const db::Device &a, const db::Device & // DeviceClass class implementation DeviceClass::DeviceClass () - : mp_netlist (0) + : mp_netlist (0), m_strict (false) { // .. nothing yet .. } DeviceClass::DeviceClass (const DeviceClass &other) - : gsi::ObjectBase (other), tl::Object (other), tl::UniqueId (other), mp_netlist (0) + : gsi::ObjectBase (other), tl::Object (other), tl::UniqueId (other), mp_netlist (0), m_strict (false) { operator= (other); } @@ -154,6 +154,7 @@ DeviceClass &DeviceClass::operator= (const DeviceClass &other) m_parameter_definitions = other.m_parameter_definitions; m_name = other.m_name; m_description = other.m_description; + m_strict = other.m_strict; mp_pc_delegate.reset (const_cast (other.mp_pc_delegate.get ())); } return *this; diff --git a/src/db/db/dbDeviceClass.h b/src/db/db/dbDeviceClass.h index 62530e712..ff3d96b15 100644 --- a/src/db/db/dbDeviceClass.h +++ b/src/db/db/dbDeviceClass.h @@ -350,6 +350,26 @@ public: return mp_netlist; } + /** + * @brief Sets a value indicating whether this class performs strict terminal mapping + * + * Classes with this flag set don't allow terminal swapping, independently of the + * "normalize_terminal_id" implementation. If two classes are involved in a compare, + * both classes are treated strict if one of them operates in strict mode. + */ + void set_strict (bool s) + { + m_strict = s; + } + + /** + * @brief Gets a value indicating whether this class performs strict terminal mapping + */ + bool is_strict () const + { + return m_strict; + } + /** * @brief Gets the name of the device class * @@ -555,6 +575,7 @@ private: std::string m_name, m_description; std::vector m_terminal_definitions; std::vector m_parameter_definitions; + bool m_strict; db::Netlist *mp_netlist; tl::shared_ptr mp_pc_delegate; diff --git a/src/db/db/dbLayoutToNetlist.cc b/src/db/db/dbLayoutToNetlist.cc index bb7399b35..b30dfb26a 100644 --- a/src/db/db/dbLayoutToNetlist.cc +++ b/src/db/db/dbLayoutToNetlist.cc @@ -1148,7 +1148,7 @@ db::Region LayoutToNetlist::antenna_check (const db::Region &gate, const db::Reg } -void db::LayoutToNetlist::save (const std::string &path, bool short_format) +void LayoutToNetlist::save (const std::string &path, bool short_format) { tl::OutputStream stream (path); db::LayoutToNetlistStandardWriter writer (stream, short_format); @@ -1156,7 +1156,7 @@ void db::LayoutToNetlist::save (const std::string &path, bool short_format) writer.write (this); } -void db::LayoutToNetlist::load (const std::string &path) +void LayoutToNetlist::load (const std::string &path) { tl::InputStream stream (path); db::LayoutToNetlistStandardReader reader (stream); @@ -1165,7 +1165,7 @@ void db::LayoutToNetlist::load (const std::string &path) reader.read (this); } -db::LayoutToNetlist *db::LayoutToNetlist::create_from_file (const std::string &path) +db::LayoutToNetlist *LayoutToNetlist::create_from_file (const std::string &path) { std::auto_ptr db; @@ -1189,4 +1189,9 @@ db::LayoutToNetlist *db::LayoutToNetlist::create_from_file (const std::string &p return db.release (); } +void LayoutToNetlist::set_generator (const std::string &g) +{ + m_generator = g; +} + } diff --git a/src/db/db/dbLayoutToNetlist.h b/src/db/db/dbLayoutToNetlist.h index e2287a301..3b31ddff3 100644 --- a/src/db/db/dbLayoutToNetlist.h +++ b/src/db/db/dbLayoutToNetlist.h @@ -254,6 +254,19 @@ public: */ std::string name (unsigned int) const; + /** + * @brief Sets the generator string + */ + void set_generator (const std::string &g); + + /** + * @brief Gets the generator string + */ + const std::string &generator () const + { + return m_generator; + } + /** * @brief Returns true, if the region is a persisted region * Persisted regions have a name and are kept inside the LayoutToNetlist @@ -730,6 +743,7 @@ private: bool m_is_flat; double m_device_scaling; db::DeepLayer m_dummy_layer; + std::string m_generator; struct CellReuseTableKey { diff --git a/src/db/db/dbLayoutVsSchematic.cc b/src/db/db/dbLayoutVsSchematic.cc index e6c092795..fc054d6f5 100644 --- a/src/db/db/dbLayoutVsSchematic.cc +++ b/src/db/db/dbLayoutVsSchematic.cc @@ -86,7 +86,7 @@ db::NetlistCrossReference *LayoutVsSchematic::make_cross_ref () } -void db::LayoutVsSchematic::save (const std::string &path, bool short_format) +void LayoutVsSchematic::save (const std::string &path, bool short_format) { tl::OutputStream stream (path); db::LayoutVsSchematicStandardWriter writer (stream, short_format); @@ -94,7 +94,7 @@ void db::LayoutVsSchematic::save (const std::string &path, bool short_format) writer.write (this); } -void db::LayoutVsSchematic::load (const std::string &path) +void LayoutVsSchematic::load (const std::string &path) { tl::InputStream stream (path); db::LayoutVsSchematicStandardReader reader (stream); diff --git a/src/db/db/dbNet.h b/src/db/db/dbNet.h index ada3e98e2..dd476652a 100644 --- a/src/db/db/dbNet.h +++ b/src/db/db/dbNet.h @@ -603,11 +603,11 @@ public: } /** - * @brief Returns true, if the net is floating (has no or only a single connection) + * @brief Returns true, if the net is floating (there is no active element on the net) */ bool is_floating () const { - return (m_pins.size () + m_subcircuit_pins.size () + m_terminals.size ()) < 2; + return (m_subcircuit_pins.size () + m_terminals.size ()) < 1; } /** diff --git a/src/db/db/dbNetlistCompare.cc b/src/db/db/dbNetlistCompare.cc index dbcb61d3c..1124dae2d 100644 --- a/src/db/db/dbNetlistCompare.cc +++ b/src/db/db/dbNetlistCompare.cc @@ -447,6 +447,24 @@ public: { return generic_categorizer::cat_for (cls); } + + void clear_strict_device_categories () + { + m_strict_device_categories.clear (); + } + + void set_strict_device_category (size_t cat) + { + m_strict_device_categories.insert (cat); + } + + bool is_strict_device_category (size_t cat) const + { + return m_strict_device_categories.find (cat) != m_strict_device_categories.end (); + } + +private: + std::set m_strict_device_categories; }; // -------------------------------------------------------------------------------------------------------------------- @@ -505,12 +523,13 @@ class NetGraph; struct CompareData { CompareData () - : other (0), max_depth (0), max_n_branch (0), logger (0), circuit_pin_mapper (0) + : other (0), max_depth (0), max_n_branch (0), dont_consider_net_names (false), logger (0), circuit_pin_mapper (0) { } NetGraph *other; size_t max_depth; size_t max_n_branch; + bool dont_consider_net_names; NetlistCompareLogger *logger; CircuitPinMapper *circuit_pin_mapper; }; @@ -714,7 +733,14 @@ public: // .. nothing yet .. } + /** + * @brief Builds a node for a net + */ NetGraphNode (const db::Net *net, DeviceCategorizer &device_categorizer, CircuitCategorizer &circuit_categorizer, const DeviceFilter &device_filter, const std::map *circuit_map, const CircuitPinMapper *pin_map); + + /** + * @brief Builds a virtual node for a subcircuit + */ NetGraphNode (const db::SubCircuit *sc, CircuitCategorizer &circuit_categorizer, const std::map *circuit_map, const CircuitPinMapper *pin_map); void expand_subcircuit_nodes (NetGraph *graph); @@ -984,7 +1010,7 @@ public: * with a proposed identity. With "with_ambiguous", amiguities are resolved by trying * different combinations in tentative mode and deciding for one combination if possible. */ - size_t derive_node_identities_from_node_set (const std::vector &nodes, const std::vector &other_nodes, size_t depth, size_t n_branch, TentativeNodeMapping *tentative, bool with_ambiguous, CompareData *data); + size_t derive_node_identities_from_node_set (std::vector &nodes, std::vector &other_nodes, size_t depth, size_t n_branch, TentativeNodeMapping *tentative, bool with_ambiguous, CompareData *data); private: std::vector m_nodes; @@ -1070,17 +1096,23 @@ NetGraphNode::NetGraphNode (const db::Net *net, DeviceCategorizer &device_catego continue; } - size_t terminal1_id = translate_terminal_id (i->terminal_id (), d); + bool is_strict = device_categorizer.is_strict_device_category (device_cat); + + // strict device checking means no terminal swapping + size_t terminal1_id = is_strict ? i->terminal_id () : translate_terminal_id (i->terminal_id (), d); const std::vector &td = d->device_class ()->terminal_definitions (); for (std::vector::const_iterator it = td.begin (); it != td.end (); ++it) { if (it->id () != i->terminal_id ()) { - size_t terminal2_id = translate_terminal_id (it->id (), d); + size_t terminal2_id = is_strict ? it->id () : translate_terminal_id (it->id (), d); Transition ed2 (d, device_cat, terminal1_id, terminal2_id); const db::Net *net2 = d->net_for_terminal (it->id ()); + if (! net2) { + continue; + } std::map::const_iterator in = n2entry.find ((const void *) net2); if (in == n2entry.end ()) { @@ -1117,6 +1149,9 @@ NetGraphNode::NetGraphNode (const db::SubCircuit *sc, CircuitCategorizer &circui size_t pin_id = p->id (); const db::Net *net_at_pin = sc->net_for_pin (pin_id); + if (! net_at_pin) { + continue; + } // A pin assignment may be missing because there is no net for a pin -> skip this @@ -1348,7 +1383,7 @@ NetGraphNode::edge_equal (const db::Net *a, const db::Net *b) */ struct NodeRange { - NodeRange (size_t _num, std::vector::const_iterator _n1, std::vector::const_iterator _nn1, std::vector::const_iterator _n2, std::vector::const_iterator _nn2) + NodeRange (size_t _num, std::vector::iterator _n1, std::vector::iterator _nn1, std::vector::iterator _n2, std::vector::iterator _nn2) : num (_num), n1 (_n1), nn1 (_nn1), n2 (_n2), nn2 (_nn2) { // .. nothing yet .. @@ -1360,7 +1395,7 @@ struct NodeRange } size_t num; - std::vector::const_iterator n1, nn1, n2, nn2; + std::vector::iterator n1, nn1, n2, nn2; }; // -------------------------------------------------------------------------------------------------------------------- @@ -1646,8 +1681,81 @@ NetGraph::derive_node_identities (size_t net_index, size_t depth, size_t n_branc return new_nodes; } +namespace { + + struct SortNodeByNet + { + public: + bool operator() (const NetGraphNode *a, const NetGraphNode *b) const + { + tl_assert (a->net () && b->net ()); + return a->net ()->name () < b->net ()->name (); + } + }; + +} + +static void sort_node_range_by_best_match (NodeRange &nr) +{ + std::stable_sort (nr.n1, nr.nn1, SortNodeByNet ()); + std::stable_sort (nr.n2, nr.nn2, SortNodeByNet ()); + + std::vector nomatch1, nomatch2; + nomatch1.reserve (nr.nn1 - nr.n1); + nomatch2.reserve (nr.nn2 - nr.n2); + + std::vector::const_iterator i = nr.n1, j = nr.n2; + std::vector::iterator iw = nr.n1, jw = nr.n2; + + SortNodeByNet compare; + + while (i != nr.nn1 || j != nr.nn2) { + if (j == nr.nn2) { + nomatch1.push_back (*i); + ++i; + } else if (i == nr.nn1) { + nomatch2.push_back (*j); + ++j; + } else if (compare (*i, *j)) { + nomatch1.push_back (*i); + ++i; + } else if (compare (*j, *i)) { + nomatch2.push_back (*j); + ++j; + } else { + if (iw != i) { + *iw = *i; + } + ++iw, ++i; + if (jw != j) { + *jw = *j; + } + ++jw, ++j; + } + } + + tl_assert (iw + nomatch1.size () == nr.nn1); + tl_assert (jw + nomatch2.size () == nr.nn2); + + for (i = nomatch1.begin (); i != nomatch1.end (); ++i) { + *iw++ = *i; + } + for (j = nomatch2.begin (); j != nomatch2.end (); ++j) { + *jw++ = *j; + } +} + +static bool net_names_are_different (const db::Net *a, const db::Net *b) +{ + if (! a || ! b || a->name ().empty () || b->name ().empty ()) { + return false; + } else { + return (a->name () != b->name ()); + } +} + size_t -NetGraph::derive_node_identities_from_node_set (const std::vector &nodes, const std::vector &other_nodes, size_t depth, size_t n_branch, TentativeNodeMapping *tentative, bool with_ambiguous, CompareData *data) +NetGraph::derive_node_identities_from_node_set (std::vector &nodes, std::vector &other_nodes, size_t depth, size_t n_branch, TentativeNodeMapping *tentative, bool with_ambiguous, CompareData *data) { #if defined(PRINT_DEBUG_NETCOMPARE) std::string indent; @@ -1723,8 +1831,8 @@ NetGraph::derive_node_identities_from_node_set (const std::vector node_ranges; - std::vector::const_iterator n1 = nodes.begin (); - std::vector::const_iterator n2 = other_nodes.begin (); + std::vector::iterator n1 = nodes.begin (); + std::vector::iterator n2 = other_nodes.begin (); while (n1 != nodes.end () && n2 != other_nodes.end ()) { @@ -1744,7 +1852,7 @@ NetGraph::derive_node_identities_from_node_set (const std::vector::const_iterator nn1 = n1, nn2 = n2; + std::vector::iterator nn1 = n1, nn2 = n2; size_t num = 1; ++nn1; @@ -1819,6 +1927,16 @@ NetGraph::derive_node_identities_from_node_set (const std::vectorn1)->has_other () && ! (*nr->n2)->has_other ()) { + // in tentative mode, reject this choice if both nets are named and + // their names differ -> this favors net matching by name + + if (tentative && ! data->dont_consider_net_names && net_names_are_different ((*nr->n1)->net (), (*nr->n2)->net ())) { +#if defined(PRINT_DEBUG_NETCOMPARE) + tl::info << indent << "rejecting pair as names are not identical: " << (*nr->n1)->net ()->expanded_name () << " vs. " << (*nr->n2)->net ()->expanded_name (); +#endif + return std::numeric_limits::max (); + } + // A single candiate: just take this one -> this may render // inexact matches, but further propagates net pairing @@ -1875,10 +1993,17 @@ NetGraph::derive_node_identities_from_node_set (const std::vectornum << " members"; #endif + + // sort the ambiguity group such that net names + std::vector > pairs; tl::equivalence_clusters equivalent_other_nodes; std::set seen; + if (! data->dont_consider_net_names) { + sort_node_range_by_best_match (*nr); + } + for (std::vector::const_iterator i1 = nr->n1; i1 != nr->nn1; ++i1) { if ((*i1)->has_other ()) { @@ -2027,6 +2152,8 @@ NetlistComparer::NetlistComparer (NetlistCompareLogger *logger) m_max_depth = 8; m_max_n_branch = 100; + + m_dont_consider_net_names = false; } NetlistComparer::~NetlistComparer () @@ -2104,14 +2231,14 @@ NetlistComparer::unmatched_circuits (db::Netlist *a, db::Netlist *b, std::vector for (db::Netlist::circuit_iterator i = a->begin_circuits (); i != a->end_circuits (); ++i) { size_t cat = circuit_categorizer.cat_for_circuit (i.operator-> ()); - if (cat && i->begin_refs () != i->end_refs ()) { + if (cat) { cat2circuits[cat].first = i.operator-> (); } } for (db::Netlist::circuit_iterator i = b->begin_circuits (); i != b->end_circuits (); ++i) { size_t cat = circuit_categorizer.cat_for_circuit (i.operator-> ()); - if (cat && i->begin_refs () != i->end_refs ()) { + if (cat) { cat2circuits[cat].second = i.operator-> (); } } @@ -2203,6 +2330,16 @@ NetlistComparer::compare (const db::Netlist *a, const db::Netlist *b) const } } + // device whether to use a device category in strict mode + + device_categorizer.clear_strict_device_categories (); + + for (std::map >::const_iterator i = cat2dc.begin (); i != cat2dc.end (); ++i) { + if (i->second.first && i->second.second && (i->second.first->is_strict () || i->second.second->is_strict ())) { + device_categorizer.set_strict_device_category (i->first); + } + } + // check for circuits that don't match for (std::map >::const_iterator i = cat2circuits.begin (); i != cat2circuits.end (); ++i) { @@ -2333,13 +2470,13 @@ NetlistComparer::all_subcircuits_verified (const db::Circuit *c, const std::set< } static std::vector > -compute_device_key (const db::Device &device, const db::NetGraph &g) +compute_device_key (const db::Device &device, const db::NetGraph &g, bool strict) { std::vector > k; const std::vector &td = device.device_class ()->terminal_definitions (); for (std::vector::const_iterator t = td.begin (); t != td.end (); ++t) { - size_t terminal_id = translate_terminal_id (t->id (), &device); + size_t terminal_id = strict ? t->id () : translate_terminal_id (t->id (), &device); const db::Net *net = device.net_for_terminal (t->id ()); size_t net_id = g.node_index_for_net (net); k.push_back (std::make_pair (terminal_id, net_id)); @@ -2573,6 +2710,7 @@ NetlistComparer::compare_circuits (const db::Circuit *c1, const db::Circuit *c2, data.other = &g2; data.max_depth = m_max_depth; data.max_n_branch = m_max_n_branch; + data.dont_consider_net_names = m_dont_consider_net_names; data.circuit_pin_mapper = &circuit_pin_mapper; data.logger = mp_logger; @@ -2625,6 +2763,7 @@ NetlistComparer::compare_circuits (const db::Circuit *c1, const db::Circuit *c2, data.other = &g2; data.max_depth = m_max_depth; data.max_n_branch = m_max_n_branch; + data.dont_consider_net_names = m_dont_consider_net_names; data.circuit_pin_mapper = &circuit_pin_mapper; data.logger = mp_logger; @@ -2666,186 +2805,170 @@ NetlistComparer::compare_circuits (const db::Circuit *c1, const db::Circuit *c2, return good; } +void +NetlistComparer::handle_pin_mismatch (const db::Circuit *c1, const db::Pin *pin1, const db::Circuit *c2, const db::Pin *pin2, bool &good, bool &pin_mismatch) const +{ + // Determine whether the pin in question is used - only in this case we will report an error. + // Otherwise, the report will be "match" against 0. + + const db::Circuit *c = pin1 ? c1 : c2; + const db::Pin *pin = pin1 ? pin1 : pin2; + + bool is_not_connected = true; + for (db::Circuit::const_refs_iterator r = c->begin_refs (); r != c->end_refs () && is_not_connected; ++r) { + const db::SubCircuit *sc = r.operator-> (); + const db::Net *net = sc->net_for_pin (pin->id ()); + if (net && ((net->terminal_count () + net->pin_count ()) > 0 || net->subcircuit_pin_count () > 1)) { + is_not_connected = false; + } + } + + if (is_not_connected) { + if (mp_logger) { + mp_logger->match_pins (pin1, pin2); + } + } else { + if (mp_logger) { + mp_logger->pin_mismatch (pin1, pin2); + } + good = false; + pin_mismatch = true; + } +} + void NetlistComparer::do_pin_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, std::map &c12_circuit_and_pin_mapping, std::map &c22_circuit_and_pin_mapping, bool &pin_mismatch, bool &good) const { // Report pin assignment // This step also does the pin identity mapping. - if (c1->pin_count () > 0 && c2->pin_count () > 0) { + // try to assign floating pins by name with higher prio + std::map > floating_pins_by_name; - // try to assign floating pins by name with higher prio - std::map > floating_pins_by_name; - - for (db::Circuit::const_pin_iterator p = c2->begin_pins (); p != c2->end_pins (); ++p) { - const db::Net *net = c2->net_for_pin (p->id ()); - if (!net && !p->name ().empty ()) { - floating_pins_by_name.insert (std::make_pair (normalize_name (p->name ()), std::make_pair ((const db::Pin *) 0, (const db::Pin *) 0))).first->second.second = p.operator-> (); - } + for (db::Circuit::const_pin_iterator p = c2->begin_pins (); p != c2->end_pins (); ++p) { + const db::Net *net = c2->net_for_pin (p->id ()); + if (!net && !p->name ().empty ()) { + floating_pins_by_name.insert (std::make_pair (normalize_name (p->name ()), std::make_pair ((const db::Pin *) 0, (const db::Pin *) 0))).first->second.second = p.operator-> (); } + } - for (db::Circuit::const_pin_iterator p = c1->begin_pins (); p != c1->end_pins (); ++p) { - const db::Net *net = c1->net_for_pin (p->id ()); - if (!net && !p->name ().empty ()) { - floating_pins_by_name.insert (std::make_pair (normalize_name (p->name ()), std::make_pair ((const db::Pin *) 0, (const db::Pin *) 0))).first->second.first = p.operator-> (); - } + for (db::Circuit::const_pin_iterator p = c1->begin_pins (); p != c1->end_pins (); ++p) { + const db::Net *net = c1->net_for_pin (p->id ()); + if (!net && !p->name ().empty ()) { + floating_pins_by_name.insert (std::make_pair (normalize_name (p->name ()), std::make_pair ((const db::Pin *) 0, (const db::Pin *) 0))).first->second.first = p.operator-> (); } + } - std::map floating_pin_name_mapping; - for (std::map >::const_iterator i = floating_pins_by_name.begin (); i != floating_pins_by_name.end (); ++i) { - if (i->second.first && i->second.second) { - floating_pin_name_mapping [i->second.first] = i->second.second; - floating_pin_name_mapping [i->second.second] = i->second.first; - } + std::map floating_pin_name_mapping; + for (std::map >::const_iterator i = floating_pins_by_name.begin (); i != floating_pins_by_name.end (); ++i) { + if (i->second.first && i->second.second) { + floating_pin_name_mapping [i->second.first] = i->second.second; + floating_pin_name_mapping [i->second.second] = i->second.first; } + } - std::vector floating_pins; - std::multimap net2pin; - for (db::Circuit::const_pin_iterator p = c2->begin_pins (); p != c2->end_pins (); ++p) { - const db::Net *net = c2->net_for_pin (p->id ()); - if (net) { - net2pin.insert (std::make_pair (g2.node_index_for_net (net), p.operator-> ())); - } else if (floating_pin_name_mapping.find (p.operator-> ()) == floating_pin_name_mapping.end ()) { - floating_pins.push_back (p.operator-> ()); - } + std::vector floating_pins; + std::multimap net2pin; + for (db::Circuit::const_pin_iterator p = c2->begin_pins (); p != c2->end_pins (); ++p) { + const db::Net *net = c2->net_for_pin (p->id ()); + if (net) { + net2pin.insert (std::make_pair (g2.node_index_for_net (net), p.operator-> ())); + } else if (floating_pin_name_mapping.find (p.operator-> ()) == floating_pin_name_mapping.end ()) { + floating_pins.push_back (p.operator-> ()); } + } - std::vector::iterator next_float = floating_pins.begin (); + std::vector::iterator next_float = floating_pins.begin (); - CircuitMapper &c12_pin_mapping = c12_circuit_and_pin_mapping [c1]; - c12_pin_mapping.set_other (c2); + CircuitMapper &c12_pin_mapping = c12_circuit_and_pin_mapping [c1]; + c12_pin_mapping.set_other (c2); - // dummy mapping: we show this circuit is used. - CircuitMapper &c22_pin_mapping = c22_circuit_and_pin_mapping [c2]; - c22_pin_mapping.set_other (c2); + // dummy mapping: we show this circuit is used. + CircuitMapper &c22_pin_mapping = c22_circuit_and_pin_mapping [c2]; + c22_pin_mapping.set_other (c2); - for (db::Circuit::const_pin_iterator p = c1->begin_pins (); p != c1->end_pins (); ++p) { + for (db::Circuit::const_pin_iterator p = c1->begin_pins (); p != c1->end_pins (); ++p) { - const db::Net *net = c1->net_for_pin (p->id ()); - if (! net) { + const db::Net *net = c1->net_for_pin (p->id ()); + if (! net) { - std::map::const_iterator fp = floating_pin_name_mapping.find (p.operator-> ()); - if (fp != floating_pin_name_mapping.end ()) { - - // assign a floating pin - this is a dummy assignment which is mitigated - // by declaring the pins equivalent in derive_pin_equivalence - if (mp_logger) { - mp_logger->match_pins (p.operator-> (), fp->second); - } - c12_pin_mapping.map_pin (p->id (), fp->second->id ()); - c22_pin_mapping.map_pin (fp->second->id (), p->id ()); - - } else if (next_float != floating_pins.end ()) { - - // assign a floating pin - this is a dummy assignment which is mitigated - // by declaring the pins equivalent in derive_pin_equivalence - if (mp_logger) { - mp_logger->match_pins (p.operator-> (), *next_float); - } - c12_pin_mapping.map_pin (p->id (), (*next_float)->id ()); - c22_pin_mapping.map_pin ((*next_float)->id (), p->id ()); - - ++next_float; - - } else { - - // otherwise this is an error - if (mp_logger) { - mp_logger->pin_mismatch (p.operator-> (), 0); - } - - pin_mismatch = true; - good = false; + std::map::const_iterator fp = floating_pin_name_mapping.find (p.operator-> ()); + if (fp != floating_pin_name_mapping.end ()) { + // assign a floating pin - this is a dummy assignment which is mitigated + // by declaring the pins equivalent in derive_pin_equivalence + if (mp_logger) { + mp_logger->match_pins (p.operator-> (), fp->second); } + c12_pin_mapping.map_pin (p->id (), fp->second->id ()); + c22_pin_mapping.map_pin (fp->second->id (), p->id ()); - continue; + } else if (next_float != floating_pins.end ()) { + + // assign a floating pin - this is a dummy assignment which is mitigated + // by declaring the pins equivalent in derive_pin_equivalence + if (mp_logger) { + mp_logger->match_pins (p.operator-> (), *next_float); + } + c12_pin_mapping.map_pin (p->id (), (*next_float)->id ()); + c22_pin_mapping.map_pin ((*next_float)->id (), p->id ()); + + ++next_float; + + } else { + + // otherwise this is an error for subcircuits or worth a report for top-level circuits + handle_pin_mismatch (c1, p.operator-> (), c2, 0, good, pin_mismatch); } - const db::NetGraphNode &n = *(g1.begin () + g1.node_index_for_net (net)); + continue; - if (! n.has_other ()) { + } + + const db::NetGraphNode &n = *(g1.begin () + g1.node_index_for_net (net)); + + if (! n.has_other ()) { + + handle_pin_mismatch (c1, p.operator-> (), c2, 0, good, pin_mismatch); + + continue; + + } + + std::multimap::iterator np = net2pin.find (n.other_net_index ()); + for (db::Net::const_pin_iterator pi = net->begin_pins (); pi != net->end_pins (); ++pi) { + + if (np != net2pin.end () && np->first == n.other_net_index ()) { if (mp_logger) { - mp_logger->pin_mismatch (p.operator-> (), 0); + mp_logger->match_pins (pi->pin (), np->second); } + c12_pin_mapping.map_pin (pi->pin ()->id (), np->second->id ()); + // dummy mapping: we show this pin is used. + c22_pin_mapping.map_pin (np->second->id (), np->second->id ()); - pin_mismatch = true; - good = false; + std::multimap::iterator np_delete = np; + ++np; + net2pin.erase (np_delete); - continue; + } else { - } - - std::multimap::iterator np = net2pin.find (n.other_net_index ()); - for (db::Net::const_pin_iterator pi = net->begin_pins (); pi != net->end_pins (); ++pi) { - - if (np != net2pin.end () && np->first == n.other_net_index ()) { - - if (mp_logger) { - mp_logger->match_pins (pi->pin (), np->second); - } - c12_pin_mapping.map_pin (pi->pin ()->id (), np->second->id ()); - // dummy mapping: we show this pin is used. - c22_pin_mapping.map_pin (np->second->id (), np->second->id ()); - - std::multimap::iterator np_delete = np; - ++np; - net2pin.erase (np_delete); - - } else { - - if (mp_logger) { - mp_logger->pin_mismatch (pi->pin (), 0); - } - pin_mismatch = true; - good = false; - - } + handle_pin_mismatch (c1, pi->pin (), c2, 0, good, pin_mismatch); } } - for (std::multimap::iterator np = net2pin.begin (); np != net2pin.end (); ++np) { - if (mp_logger) { - mp_logger->pin_mismatch (0, np->second); - } - pin_mismatch = true; - good = false; - } + } - while (next_float != floating_pins.end ()) { - if (mp_logger) { - mp_logger->pin_mismatch (0, *next_float); - } - pin_mismatch = true; - good = false; - ++next_float; - } - - } else { - - // skip pin mapping in case one circuit does not feature pins - // This is often the case for top-level circuits. We don't necessarily need pins for them. - // We still report those circuits with "pin mismatch" so they don't get considered within - // subcircuits. Plus we report the pins so they get listed in the cross-ref (but with a - // "match" - this is important to cover the cases which are found when analyzing the nets). - - if (mp_logger) { - for (db::Circuit::const_pin_iterator p = c1->begin_pins (); p != c1->end_pins (); ++p) { - mp_logger->match_pins (p.operator-> (), 0); - } - for (db::Circuit::const_pin_iterator p = c2->begin_pins (); p != c2->end_pins (); ++p) { - mp_logger->match_pins (0, p.operator-> ()); - } - } - - if (c1->pin_count () != c2->pin_count ()) { - pin_mismatch = true; - } + for (std::multimap::iterator np = net2pin.begin (); np != net2pin.end (); ++np) { + handle_pin_mismatch (c1, 0, c2, np->second, good, pin_mismatch); + } + while (next_float != floating_pins.end ()) { + handle_pin_mismatch (c1, 0, c2, *next_float, good, pin_mismatch); + ++next_float; } } @@ -2872,7 +2995,7 @@ NetlistComparer::do_device_assignment (const db::Circuit *c1, const db::NetGraph continue; } - std::vector > k = compute_device_key (*d, g1); + std::vector > k = compute_device_key (*d, g1, device_categorizer.is_strict_device_category (device_cat)); bool mapped = true; for (std::vector >::iterator i = k.begin (); i != k.end (); ++i) { @@ -2906,7 +3029,7 @@ NetlistComparer::do_device_assignment (const db::Circuit *c1, const db::NetGraph continue; } - std::vector > k = compute_device_key (*d, g2); + std::vector > k = compute_device_key (*d, g2, device_categorizer.is_strict_device_category (device_cat)); bool mapped = true; for (std::vector >::iterator i = k.begin (); i != k.end (); ++i) { @@ -2999,14 +3122,12 @@ NetlistComparer::do_device_assignment (const db::Circuit *c1, const db::NetGraph ++i; } - if (i == unmatched_a.end () && j == unmatched_b.end ()) { + if (i == unmatched_a.end () || j == unmatched_b.end ()) { break; } unmatched_list::iterator ii = i, jj = j; ++i, ++j; - size_t n = ii->first.size (); - tl_assert (n == jj->first.size ()); while (i != unmatched_a.end () && cmp.equals (*i, *ii)) { ++i; @@ -3167,7 +3288,7 @@ NetlistComparer::do_subcircuit_assignment (const db::Circuit *c1, const db::NetG ++i; } - if (i == unmatched_a.end () && j == unmatched_b.end ()) { + if (i == unmatched_a.end () || j == unmatched_b.end ()) { break; } diff --git a/src/db/db/dbNetlistCompare.h b/src/db/db/dbNetlistCompare.h index 774936442..bcb6b9f56 100644 --- a/src/db/db/dbNetlistCompare.h +++ b/src/db/db/dbNetlistCompare.h @@ -245,6 +245,23 @@ public: return m_max_depth; } + /** + * @brief Sets a value indicating whether not to consider net names + * This feature is mainly intended for testing. + */ + void set_dont_consider_net_names (bool f) + { + m_dont_consider_net_names = f; + } + + /** + * @brief Gets a value indicating whether not to consider net names + */ + bool dont_consider_net_names () const + { + return m_dont_consider_net_names; + } + /** * @brief Sets the maximum branch complexity * @@ -297,6 +314,7 @@ protected: void do_pin_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, std::map &c12_circuit_and_pin_mapping, std::map &c22_circuit_and_pin_mapping, bool &pin_mismatch, bool &good) const; void do_device_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, const db::DeviceFilter &device_filter, DeviceCategorizer &device_categorizer, bool &good) const; void do_subcircuit_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, CircuitCategorizer &circuit_categorizer, const db::CircuitPinMapper &circuit_pin_mapper, std::map &c12_circuit_and_pin_mapping, std::map &c22_circuit_and_pin_mapping, bool &good) const; + void handle_pin_mismatch (const db::Circuit *c1, const db::Pin *pin1, const db::Circuit *c2, const db::Pin *p2, bool &good, bool &pin_mismatch) const; mutable NetlistCompareLogger *mp_logger; std::map, std::vector > > m_same_nets; @@ -307,6 +325,7 @@ protected: double m_res_threshold; size_t m_max_n_branch; size_t m_max_depth; + bool m_dont_consider_net_names; }; } diff --git a/src/db/db/dbNetlistDeviceExtractorClasses.cc b/src/db/db/dbNetlistDeviceExtractorClasses.cc index 394c74bad..01406124e 100644 --- a/src/db/db/dbNetlistDeviceExtractorClasses.cc +++ b/src/db/db/dbNetlistDeviceExtractorClasses.cc @@ -30,114 +30,252 @@ namespace db // --------------------------------------------------------------------------------- // NetlistDeviceExtractorMOS3Transistor implementation -NetlistDeviceExtractorMOS3Transistor::NetlistDeviceExtractorMOS3Transistor (const std::string &name) - : db::NetlistDeviceExtractor (name) +NetlistDeviceExtractorMOS3Transistor::NetlistDeviceExtractorMOS3Transistor (const std::string &name, bool strict) + : db::NetlistDeviceExtractor (name), + m_strict (strict) { // .. nothing yet .. } void NetlistDeviceExtractorMOS3Transistor::setup () { - define_layer ("SD", "Source/drain diffusion"); // #0 - define_layer ("G", "Gate input"); // #1 - // for backward compatibility - define_layer ("P", 1, "Gate terminal output"); // #2 -> G + if (! is_strict ()) { - // terminal output - define_layer ("tG", 2, "Gate terminal output"); // #3 -> P -> G - define_layer ("tS", 0, "Source terminal output (default is SD)"); // #4 - define_layer ("tD", 0, "Drain terminal output (default is SD)"); // #5 + define_layer ("SD", "Source/drain diffusion"); // #0 + define_layer ("G", "Gate input"); // #1 + // for backward compatibility + define_layer ("P", 1, "Gate terminal output"); // #2 -> G - register_device_class (new db::DeviceClassMOS3Transistor ()); + // terminal output + define_layer ("tG", 2, "Gate terminal output"); // #3 -> P -> G + define_layer ("tS", 0, "Source terminal output (default is SD)"); // #4 + define_layer ("tD", 0, "Drain terminal output (default is SD)"); // #5 + + } else { + + define_layer ("S", "Source diffusion"); // #0 + define_layer ("D", "Drain diffusion"); // #1 + define_layer ("G", "Gate input"); // #2 + // for backward compatibility + define_layer ("P", 2, "Gate terminal output"); // #3 -> G + + // terminal output + define_layer ("tG", 3, "Gate terminal output"); // #4 -> P -> G + define_layer ("tS", 0, "Source terminal output (default is S)"); // #5 + define_layer ("tD", 1, "Drain terminal output (default is D)"); // #6 + + } + + db::DeviceClass *cls = new db::DeviceClassMOS3Transistor (); + cls->set_strict (m_strict); + register_device_class (cls); } db::Connectivity NetlistDeviceExtractorMOS3Transistor::get_connectivity (const db::Layout & /*layout*/, const std::vector &layers) const { - tl_assert (layers.size () >= 3); + if (! is_strict ()) { - unsigned int diff = layers [0]; - unsigned int gate = layers [1]; - // not used for device recognition: poly (2), but used for producing the gate terminals + tl_assert (layers.size () >= 3); - // The layer definition is diff, gate - db::Connectivity conn; - // collect all connected diffusion shapes - conn.connect (diff, diff); - // collect all connected gate shapes - conn.connect (gate, gate); - // connect gate with diff to detect gate/diffusion boundary - conn.connect (diff, gate); - return conn; + unsigned int diff = layers [0]; + unsigned int gate = layers [1]; + + // The layer definition is diff, gate + db::Connectivity conn; + // collect all connected diffusion shapes + conn.connect (diff, diff); + // collect all connected gate shapes + conn.connect (gate, gate); + // connect gate with diff to detect gate/diffusion boundary + conn.connect (diff, gate); + return conn; + + } else { + + + tl_assert (layers.size () >= 4); + + unsigned int sdiff = layers [0]; + unsigned int ddiff = layers [1]; + unsigned int gate = layers [2]; + + // The layer definition is diff, gate + db::Connectivity conn; + // collect all connected diffusion shapes + conn.connect (sdiff, sdiff); + conn.connect (ddiff, ddiff); + // collect all connected gate shapes + conn.connect (gate, gate); + // connect gate with diff to detect gate/diffusion boundary + conn.connect (sdiff, gate); + conn.connect (ddiff, gate); + return conn; + + } } void NetlistDeviceExtractorMOS3Transistor::extract_devices (const std::vector &layer_geometry) { - unsigned int diff_geometry_index = 0; - unsigned int gate_geometry_index = 1; - unsigned int gate_terminal_geometry_index = 3; - unsigned int source_terminal_geometry_index = 4; - unsigned int drain_terminal_geometry_index = 5; + if (! is_strict ()) { - const db::Region &rdiff = layer_geometry [diff_geometry_index]; - const db::Region &rgates = layer_geometry [gate_geometry_index]; + // See setup() for the geometry indexes + unsigned int diff_geometry_index = 0; + unsigned int gate_geometry_index = 1; + unsigned int gate_terminal_geometry_index = 3; + unsigned int source_terminal_geometry_index = 4; + unsigned int drain_terminal_geometry_index = 5; - for (db::Region::const_iterator p = rgates.begin_merged (); !p.at_end (); ++p) { + const db::Region &rdiff = layer_geometry [diff_geometry_index]; + const db::Region &rgates = layer_geometry [gate_geometry_index]; - db::Region rgate (*p); - rgate.set_base_verbosity (rgates.base_verbosity ()); + for (db::Region::const_iterator p = rgates.begin_merged (); !p.at_end (); ++p) { - db::Region rdiff2gate = rdiff.selected_interacting (rgate); - rdiff2gate.set_base_verbosity (rdiff.base_verbosity ()); + db::Region rgate (*p); + rgate.set_base_verbosity (rgates.base_verbosity ()); - if (rdiff2gate.empty ()) { - error (tl::to_string (tr ("Gate shape touches no diffusion - ignored")), *p); - } else { + db::Region rdiff2gate = rdiff.selected_interacting (rgate); + rdiff2gate.set_base_verbosity (rdiff.base_verbosity ()); - if (rdiff2gate.size () != 2) { - error (tl::sprintf (tl::to_string (tr ("Expected two polygons on diff interacting with one gate shape (found %d) - gate shape ignored")), int (rdiff2gate.size ())), *p); - continue; - } + if (rdiff2gate.empty ()) { + error (tl::to_string (tr ("Gate shape touches no diffusion - ignored")), *p); + } else { - db::Edges edges (rgate.edges () & rdiff2gate.edges ()); - if (edges.size () != 2) { - error (tl::sprintf (tl::to_string (tr ("Expected two edges interacting gate/diff (found %d) - width and length may be incorrect")), int (edges.size ())), *p); - continue; - } + if (rdiff2gate.size () != 2) { + error (tl::sprintf (tl::to_string (tr ("Expected two polygons on diff interacting with one gate shape (found %d) - gate shape ignored")), int (rdiff2gate.size ())), *p); + continue; + } - if (! p->is_box ()) { - error (tl::to_string (tr ("Gate shape is not a box - width and length may be incorrect")), *p); - } + db::Edges edges (rgate.edges () & rdiff2gate.edges ()); + if (edges.size () != 2) { + error (tl::sprintf (tl::to_string (tr ("Expected two edges interacting gate/diff (found %d) - width and length may be incorrect")), int (edges.size ())), *p); + continue; + } - db::Device *device = create_device (); + if (! p->is_box ()) { + error (tl::to_string (tr ("Gate shape is not a box - width and length may be incorrect")), *p); + } - device->set_trans (db::DCplxTrans ((p->box ().center () - db::Point ()) * dbu ())); + db::Device *device = create_device (); - device->set_parameter_value (db::DeviceClassMOS3Transistor::param_id_W, sdbu () * edges.length () * 0.5); - device->set_parameter_value (db::DeviceClassMOS3Transistor::param_id_L, sdbu () * (p->perimeter () - edges.length ()) * 0.5); + device->set_trans (db::DCplxTrans ((p->box ().center () - db::Point ()) * dbu ())); - int diff_index = 0; - for (db::Region::const_iterator d = rdiff2gate.begin (); !d.at_end () && diff_index < 2; ++d, ++diff_index) { + device->set_parameter_value (db::DeviceClassMOS3Transistor::param_id_W, sdbu () * edges.length () * 0.5); + device->set_parameter_value (db::DeviceClassMOS3Transistor::param_id_L, sdbu () * (p->perimeter () - edges.length ()) * 0.5); - // count the number of gate shapes attached to this shape and distribute the area of the - // diffusion region to the number of gates - size_t n = rgates.selected_interacting (db::Region (*d)).size (); - tl_assert (n > 0); + int diff_index = 0; + for (db::Region::const_iterator d = rdiff2gate.begin (); !d.at_end () && diff_index < 2; ++d, ++diff_index) { - device->set_parameter_value (diff_index == 0 ? db::DeviceClassMOS3Transistor::param_id_AS : db::DeviceClassMOS3Transistor::param_id_AD, sdbu () * sdbu () * d->area () / double (n)); - device->set_parameter_value (diff_index == 0 ? db::DeviceClassMOS3Transistor::param_id_PS : db::DeviceClassMOS3Transistor::param_id_PD, sdbu () * d->perimeter () / double (n)); + // count the number of gate shapes attached to this shape and distribute the area of the + // diffusion region to the number of gates + size_t n = rgates.selected_interacting (db::Region (*d)).size (); + tl_assert (n > 0); - unsigned int sd_index = diff_index == 0 ? source_terminal_geometry_index : drain_terminal_geometry_index; - define_terminal (device, diff_index == 0 ? db::DeviceClassMOS3Transistor::terminal_id_S : db::DeviceClassMOS3Transistor::terminal_id_D, sd_index, *d); + device->set_parameter_value (diff_index == 0 ? db::DeviceClassMOS3Transistor::param_id_AS : db::DeviceClassMOS3Transistor::param_id_AD, sdbu () * sdbu () * d->area () / double (n)); + device->set_parameter_value (diff_index == 0 ? db::DeviceClassMOS3Transistor::param_id_PS : db::DeviceClassMOS3Transistor::param_id_PD, sdbu () * d->perimeter () / double (n)); + + unsigned int sd_index = diff_index == 0 ? source_terminal_geometry_index : drain_terminal_geometry_index; + define_terminal (device, diff_index == 0 ? db::DeviceClassMOS3Transistor::terminal_id_S : db::DeviceClassMOS3Transistor::terminal_id_D, sd_index, *d); + + } + + define_terminal (device, db::DeviceClassMOS3Transistor::terminal_id_G, gate_terminal_geometry_index, *p); + + // allow derived classes to modify the device + modify_device (*p, layer_geometry, device); + + // output the device for debugging + device_out (device, rdiff2gate, rgate); } - define_terminal (device, db::DeviceClassMOS3Transistor::terminal_id_G, gate_terminal_geometry_index, *p); + } - // allow derived classes to modify the device - modify_device (*p, layer_geometry, device); + } else { - // output the device for debugging - device_out (device, rdiff2gate, rgate); + // See setup() for the geometry indexes + unsigned int source_geometry_index = 0; + unsigned int drain_geometry_index = 1; + unsigned int gate_geometry_index = 2; + unsigned int gate_terminal_geometry_index = 4; + unsigned int source_terminal_geometry_index = 5; + unsigned int drain_terminal_geometry_index = 6; + + const db::Region &sdiff = layer_geometry [source_geometry_index]; + const db::Region &ddiff = layer_geometry [drain_geometry_index]; + const db::Region &rgates = layer_geometry [gate_geometry_index]; + + for (db::Region::const_iterator p = rgates.begin_merged (); !p.at_end (); ++p) { + + db::Region rgate (*p); + rgate.set_base_verbosity (rgates.base_verbosity ()); + + db::Region sdiff2gate = sdiff.selected_interacting (rgate); + sdiff2gate.set_base_verbosity (sdiff.base_verbosity ()); + + db::Region ddiff2gate = ddiff.selected_interacting (rgate); + ddiff2gate.set_base_verbosity (ddiff.base_verbosity ()); + + if (sdiff2gate.empty () && ddiff2gate.empty ()) { + error (tl::to_string (tr ("Gate shape touches no diffusion - ignored")), *p); + } else if (sdiff2gate.empty () || ddiff2gate.empty ()) { + error (tl::to_string (tr ("Gate shape touches a single diffusion only - ignored")), *p); + } else { + + if (sdiff2gate.size () != 1) { + error (tl::sprintf (tl::to_string (tr ("Expected one polygons on source diff interacting with one gate shape (found %d) - gate shape ignored")), int (sdiff2gate.size ())), *p); + continue; + } + + if (ddiff2gate.size () != 1) { + error (tl::sprintf (tl::to_string (tr ("Expected one polygons on drain diff interacting with one gate shape (found %d) - gate shape ignored")), int (ddiff2gate.size ())), *p); + continue; + } + + db::Region diff2gate = sdiff2gate + ddiff2gate; + + db::Edges edges (rgate.edges () & diff2gate.edges ()); + if (edges.size () != 2) { + error (tl::sprintf (tl::to_string (tr ("Expected two edges interacting gate/diff (found %d) - width and length may be incorrect")), int (edges.size ())), *p); + continue; + } + + if (! p->is_box ()) { + error (tl::to_string (tr ("Gate shape is not a box - width and length may be incorrect")), *p); + } + + db::Device *device = create_device (); + + device->set_trans (db::DCplxTrans ((p->box ().center () - db::Point ()) * dbu ())); + + device->set_parameter_value (db::DeviceClassMOS3Transistor::param_id_W, sdbu () * edges.length () * 0.5); + device->set_parameter_value (db::DeviceClassMOS3Transistor::param_id_L, sdbu () * (p->perimeter () - edges.length ()) * 0.5); + + for (int diff_index = 0; diff_index < 2; ++diff_index) { + + const db::Region *diff = diff_index == 0 ? &sdiff2gate : &ddiff2gate; + + // count the number of gate shapes attached to this shape and distribute the area of the + // diffusion region to the number of gates + size_t n = rgates.selected_interacting (*diff).size (); + tl_assert (n > 0); + + device->set_parameter_value (diff_index == 0 ? db::DeviceClassMOS3Transistor::param_id_AS : db::DeviceClassMOS3Transistor::param_id_AD, sdbu () * sdbu () * diff->area () / double (n)); + device->set_parameter_value (diff_index == 0 ? db::DeviceClassMOS3Transistor::param_id_PS : db::DeviceClassMOS3Transistor::param_id_PD, sdbu () * diff->perimeter () / double (n)); + + unsigned int sd_index = diff_index == 0 ? source_terminal_geometry_index : drain_terminal_geometry_index; + define_terminal (device, diff_index == 0 ? db::DeviceClassMOS3Transistor::terminal_id_S : db::DeviceClassMOS3Transistor::terminal_id_D, sd_index, *diff); + + } + + define_terminal (device, db::DeviceClassMOS3Transistor::terminal_id_G, gate_terminal_geometry_index, *p); + + // allow derived classes to modify the device + modify_device (*p, layer_geometry, device); + + // output the device for debugging + device_out (device, diff2gate, rgate); + + } } @@ -147,35 +285,61 @@ void NetlistDeviceExtractorMOS3Transistor::extract_devices (const std::vector G + if (! is_strict ()) { - // terminal output - define_layer ("tG", 2, "Gate terminal output"); // #3 -> P -> G - define_layer ("tS", 0, "Source terminal output (default is SD)"); // #4 - define_layer ("tD", 0, "Drain terminal output (default is SD)"); // #5 + define_layer ("SD", "Source/drain diffusion"); // #0 + define_layer ("G", "Gate input"); // #1 + // for backward compatibility + define_layer ("P", 1, "Gate terminal output"); // #2 -> G - // for backward compatibility - define_layer ("W", "Well (bulk) terminal output"); // #6 + // terminal output + define_layer ("tG", 2, "Gate terminal output"); // #3 -> P -> G + define_layer ("tS", 0, "Source terminal output (default is SD)"); // #4 + define_layer ("tD", 0, "Drain terminal output (default is SD)"); // #5 - define_layer ("tB", 6, "Well (bulk) terminal output"); // #7 -> W + // for backward compatibility + define_layer ("W", "Well (bulk) terminal output"); // #6 - register_device_class (new db::DeviceClassMOS4Transistor ()); + define_layer ("tB", 6, "Well (bulk) terminal output"); // #7 -> W + + } else { + + define_layer ("S", "Source diffusion"); // #0 + define_layer ("D", "Drain diffusion"); // #1 + define_layer ("G", "Gate input"); // #2 + // for backward compatibility + define_layer ("P", 2, "Gate terminal output"); // #3 -> G + + // terminal output + define_layer ("tG", 3, "Gate terminal output"); // #4 -> P -> G + define_layer ("tS", 0, "Source terminal output (default is S)"); // #5 + define_layer ("tD", 1, "Drain terminal output (default is D)"); // #6 + + // for backward compatibility + define_layer ("W", "Well (bulk) terminal output"); // #7 + + define_layer ("tB", 7, "Well (bulk) terminal output"); // #8 -> W + + } + + db::DeviceClass *cls = new db::DeviceClassMOS4Transistor (); + cls->set_strict (is_strict ()); + register_device_class (cls); } void NetlistDeviceExtractorMOS4Transistor::modify_device (const db::Polygon &rgate, const std::vector & /*layer_geometry*/, db::Device *device) { - unsigned int bulk_terminal_geometry_index = 7; + // see setup() for the layer indexes: + unsigned int bulk_terminal_geometry_index = is_strict () ? 8 : 7; + define_terminal (device, db::DeviceClassMOS4Transistor::terminal_id_B, bulk_terminal_geometry_index, rgate); } diff --git a/src/db/db/dbNetlistDeviceExtractorClasses.h b/src/db/db/dbNetlistDeviceExtractorClasses.h index d623bd486..0dbb0743e 100644 --- a/src/db/db/dbNetlistDeviceExtractorClasses.h +++ b/src/db/db/dbNetlistDeviceExtractorClasses.h @@ -48,12 +48,17 @@ class DB_PUBLIC NetlistDeviceExtractorMOS3Transistor : public db::NetlistDeviceExtractor { public: - NetlistDeviceExtractorMOS3Transistor (const std::string &name); + NetlistDeviceExtractorMOS3Transistor (const std::string &name, bool strict = false); virtual void setup (); virtual db::Connectivity get_connectivity (const db::Layout &layout, const std::vector &layers) const; virtual void extract_devices (const std::vector &layer_geometry); + bool is_strict () const + { + return m_strict; + } + protected: /** * @brief A callback when the device is produced @@ -72,6 +77,8 @@ protected: // .. no specific implementation .. } +private: + bool m_strict; }; /** @@ -87,7 +94,7 @@ class DB_PUBLIC NetlistDeviceExtractorMOS4Transistor : public NetlistDeviceExtractorMOS3Transistor { public: - NetlistDeviceExtractorMOS4Transistor (const std::string &name); + NetlistDeviceExtractorMOS4Transistor (const std::string &name, bool strict = false); virtual void setup (); diff --git a/src/db/db/dbNetlistSpiceReader.cc b/src/db/db/dbNetlistSpiceReader.cc index 50218d7d2..9234570c7 100644 --- a/src/db/db/dbNetlistSpiceReader.cc +++ b/src/db/db/dbNetlistSpiceReader.cc @@ -27,6 +27,8 @@ #include "tlStream.h" #include "tlLog.h" #include "tlString.h" +#include "tlFileUtils.h" +#include "tlUri.h" #include #include @@ -83,34 +85,73 @@ static db::DeviceClass *make_device_class (db::Circuit *circuit, const std::stri return cls; } -bool NetlistSpiceReaderDelegate::element (db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector &nets, const std::map ¶ms) +bool NetlistSpiceReaderDelegate::element (db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector &nets, const std::map &pv) { + std::map params = pv; + + double mult = 1.0; + std::map::const_iterator mp = params.find ("M"); + if (mp != params.end ()) { + mult = mp->second; + } + + if (mult < 1e-10) { + error (tl::sprintf (tl::to_string (tr ("Invalid multiplier value (M=%.12g) - must not be zero or negative")), mult)); + } + std::string cn = model; db::DeviceClass *cls = circuit->netlist ()->device_class_by_name (cn); if (cls) { + // use given class + } else if (element == "R") { + if (cn.empty ()) { cn = "RES"; } cls = make_device_class (circuit, cn); + + // Apply multiplier + value /= mult; + } else if (element == "L") { + if (cn.empty ()) { cn = "IND"; } cls = make_device_class (circuit, cn); + + // Apply multiplier + value /= mult; + } else if (element == "C") { + if (cn.empty ()) { cn = "CAP"; } cls = make_device_class (circuit, cn); + + // Apply multiplier + value *= mult; + } else if (element == "D") { + if (cn.empty ()) { cn = "DIODE"; } cls = make_device_class (circuit, cn); + + // Apply multiplier to "A" + std::map::iterator p; + p = params.find ("A"); + if (p != params.end ()) { + p->second *= mult; + } + } else if (element == "Q") { + if (nets.size () == 3) { if (cn.empty ()) { cn = "BJT3"; @@ -124,12 +165,29 @@ bool NetlistSpiceReaderDelegate::element (db::Circuit *circuit, const std::strin } else { error (tl::to_string (tr ("'Q' element needs to have 3 or 4 terminals"))); } + + // Apply multiplier to "AE" + std::map::iterator p; + p = params.find ("AE"); + if (p != params.end ()) { + p->second *= mult; + } + } else if (element == "M") { + if (nets.size () == 4) { if (cn.empty ()) { cn = "MOS4"; } cls = make_device_class (circuit, cn); + + // Apply multiplier to "W" + std::map::iterator p; + p = params.find ("W"); + if (p != params.end ()) { + p->second *= mult; + } + } else { error (tl::to_string (tr ("'M' element needs to have 4 terminals"))); } @@ -243,7 +301,20 @@ void NetlistSpiceReader::finish () void NetlistSpiceReader::push_stream (const std::string &path) { - tl::InputStream *istream = new tl::InputStream (path); + tl::URI current_uri (mp_stream->source ()); + tl::URI new_uri (path); + + tl::InputStream *istream; + if (current_uri.scheme ().empty () && new_uri.scheme ().empty ()) { + if (tl::is_absolute (path)) { + istream = new tl::InputStream (path); + } else { + istream = new tl::InputStream (tl::combine_path (tl::dirname (mp_stream->source ()), path)); + } + } else { + istream = new tl::InputStream (current_uri.resolved (new_uri).to_string ()); + } + m_streams.push_back (std::make_pair (istream, mp_stream.release ())); mp_stream.reset (new tl::TextInputStream (*istream)); } @@ -291,7 +362,7 @@ std::string NetlistSpiceReader::get_line () } tl::Extractor ex (l.c_str ()); - if (ex.test_without_case (".include")) { + if (ex.test_without_case (".include") || ex.test_without_case (".inc")) { std::string path = read_name_with_case (ex); @@ -346,8 +417,10 @@ bool NetlistSpiceReader::read_card () } else if (ex.test_without_case ("global")) { - std::string n = read_name (ex); - m_global_nets.push_back (n); + while (! ex.at_end ()) { + std::string n = read_name (ex); + m_global_nets.push_back (n); + } } else if (ex.test_without_case ("subckt")) { @@ -405,7 +478,7 @@ void NetlistSpiceReader::error (const std::string &msg) void NetlistSpiceReader::warn (const std::string &msg) { - std::string fmt_msg = tl::sprintf ("%s in %s, line %d", msg, mp_stream->source (), mp_stream->line_number ()); + std::string fmt_msg = tl::sprintf ("%s in %s, line %d", msg, mp_stream->source (), mp_stream->line_number () - 1); tl::warn << fmt_msg; } @@ -741,10 +814,6 @@ bool NetlistSpiceReader::read_element (tl::Extractor &ex, const std::string &ele void NetlistSpiceReader::read_subcircuit (const std::string &sc_name, const std::string &nc_name, const std::vector &nets) { - if (nets.empty ()) { - error (tl::to_string (tr ("A circuit call needs at least one net"))); - } - db::Circuit *cc = mp_netlist->circuit_by_name (nc_name); if (! cc) { diff --git a/src/db/db/gsiDeclDbCell.cc b/src/db/db/gsiDeclDbCell.cc index a68571bfe..fa1031472 100644 --- a/src/db/db/gsiDeclDbCell.cc +++ b/src/db/db/gsiDeclDbCell.cc @@ -3960,7 +3960,7 @@ Class decl_Instance ("db", "Instance", "\n" "If the instance is a PCell instance, this method will convert the cell into a static cell and " "remove the PCell variant if required. A new cell will be created containing the PCell content " - "but begin a static cell. If the instance is not a PCell instance, this method will not do anything.\n" + "but being a static cell. If the instance is not a PCell instance, this method won't do anything.\n" "\n" "This method has been introduced in version 0.24." ) + diff --git a/src/db/db/gsiDeclDbLayoutToNetlist.cc b/src/db/db/gsiDeclDbLayoutToNetlist.cc index 02ba6b3c9..c8256b0c7 100644 --- a/src/db/db/gsiDeclDbLayoutToNetlist.cc +++ b/src/db/db/gsiDeclDbLayoutToNetlist.cc @@ -169,6 +169,13 @@ Class decl_dbLayoutToNetlist ("db", "LayoutToNetlist", "The database unit is mandatory because the physical parameter extraction " "for devices requires this unit for translation of layout to physical dimensions.\n" ) + + gsi::method ("generator", &db::LayoutToNetlist::generator, + "@brief Gets the generator string.\n" + "The generator is the script that created this database.\n" + ) + + gsi::method ("generator=", &db::LayoutToNetlist::set_generator, gsi::arg ("generator"), + "@brief Sets the generator string.\n" + ) + gsi::method ("dss", (db::DeepShapeStore &(db::LayoutToNetlist::*) ()) &db::LayoutToNetlist::dss, "@brief Gets a reference to the internal DSS object.\n" ) + diff --git a/src/db/db/gsiDeclDbNetlist.cc b/src/db/db/gsiDeclDbNetlist.cc index 9523e7b7f..f229dafb1 100644 --- a/src/db/db/gsiDeclDbNetlist.cc +++ b/src/db/db/gsiDeclDbNetlist.cc @@ -809,6 +809,20 @@ Class decl_dbDeviceClass ("db", "DeviceClass", gsi::method ("name=", &db::DeviceClass::set_name, gsi::arg ("name"), "@brief Sets the name of the device class." ) + + gsi::method ("strict?", &db::DeviceClass::is_strict, + "@brief Gets a value indicating whether this class performs strict terminal mapping\n" + "See \\strict= for details about this attribute." + ) + + gsi::method ("strict=", &db::DeviceClass::set_strict, gsi::arg ("s"), + "@brief Sets a value indicating whether this class performs strict terminal mapping\n" + "\n" + "Classes with this flag set never allow terminal swapping, even if the device symmetry supports that. " + "If two classes are involved in a netlist compare,\n" + "terminal swapping will be disabled if one of the classes is in strict mode.\n" + "\n" + "By default, device classes are not strict and terminal swapping is allowed as far as the " + "device symmetry supports that." + ) + gsi::method ("description", &db::DeviceClass::description, "@brief Gets the description text of the device class." ) + @@ -1014,7 +1028,9 @@ Class decl_GenericDeviceClass (decl_dbDeviceClass, "db", "Ge gsi::method ("equivalent_terminal_id", &GenericDeviceClass::equivalent_terminal_id, gsi::arg ("original_id"), gsi::arg ("equivalent_id"), "@brief Specifies a terminal to be equivalent to another.\n" "Use this method to specify two terminals to be exchangeable. For example to make S and D of a MOS transistor equivalent, " - "call this method with S and D terminal IDs. In netlist matching, S will be translated to D and thus made equivalent to D." + "call this method with S and D terminal IDs. In netlist matching, S will be translated to D and thus made equivalent to D.\n" + "\n" + "Note that terminal equivalence is not effective if the device class operates in strict mode (see \\DeviceClass#strict=)." ), "@brief A generic device class\n" "This class allows building generic device classes. Specificially, terminals can be defined " @@ -1090,7 +1106,7 @@ Class decl_dbCircuit ("db", "Circuit", "@brief Iterates over the parent circuits of this circuit\n" "Child circuits are the ones that are referencing this circuit via subcircuits." ) + - gsi::method ("has_refs", &db::Circuit::has_refs, + gsi::method ("has_refs?", &db::Circuit::has_refs, "@brief Returns a value indicating whether the circuit has references\n" "A circuit has references if there is at least one subcircuit referring to it." ) + @@ -1363,13 +1379,13 @@ Class decl_dbNetlist ("db", "Netlist", gsi::method ("remove", &db::Netlist::remove_circuit, gsi::arg ("circuit"), "@brief Removes the given circuit object from the netlist\n" "After the circuit has been removed, the object becomes invalid and cannot be used further. " - "A circuit with references (see \\has_refs) should not be removed as the " + "A circuit with references (see \\has_refs?) should not be removed as the " "subcircuits calling it would afterwards point to nothing." ) + gsi::method ("purge_circuit", &db::Netlist::purge_circuit, gsi::arg ("circuit"), "@brief Removes the given circuit object and all child circuits which are not used otherwise from the netlist\n" "After the circuit has been removed, the object becomes invalid and cannot be used further. " - "A circuit with references (see \\has_refs) should not be removed as the " + "A circuit with references (see \\has_refs?) should not be removed as the " "subcircuits calling it would afterwards point to nothing." ) + gsi::method ("flatten_circuit", &db::Netlist::flatten_circuit, gsi::arg ("circuit"), diff --git a/src/db/db/gsiDeclDbNetlistCompare.cc b/src/db/db/gsiDeclDbNetlistCompare.cc index 0afaf06de..900df9d78 100644 --- a/src/db/db/gsiDeclDbNetlistCompare.cc +++ b/src/db/db/gsiDeclDbNetlistCompare.cc @@ -541,12 +541,10 @@ Class decl_dbNetlistComparer ("db", "NetlistComparer", gsi::method_ext ("unmatched_circuits_a", &unmatched_circuits_a, gsi::arg ("a"), gsi::arg ("b"), "@brief Returns a list of circuits in A for which there is not corresponding circuit in B\n" "This list can be used to flatten these circuits so they do not participate in the compare process.\n" - "Top level circuits are not included as they cannot be flattened.\n" ) + gsi::method_ext ("unmatched_circuits_b", &unmatched_circuits_b, gsi::arg ("a"), gsi::arg ("b"), "@brief Returns a list of circuits in B for which there is not corresponding circuit in A\n" "This list can be used to flatten these circuits so they do not participate in the compare process.\n" - "Top level circuits are not included as they cannot be flattened.\n" ) + gsi::method ("compare", (bool (db::NetlistComparer::*) (const db::Netlist *, const db::Netlist *) const) &db::NetlistComparer::compare, gsi::arg ("netlist_a"), gsi::arg ("netlist_b"), "@brief Compares two netlists.\n" diff --git a/src/db/db/gsiDeclDbNetlistDeviceExtractor.cc b/src/db/db/gsiDeclDbNetlistDeviceExtractor.cc index 0851b5f4f..9b2275b5c 100644 --- a/src/db/db/gsiDeclDbNetlistDeviceExtractor.cc +++ b/src/db/db/gsiDeclDbNetlistDeviceExtractor.cc @@ -397,14 +397,19 @@ Class decl_GenericDeviceExtractor (decl_dbNetlistDeviceE "This class has been introduced in version 0.26." ); -db::NetlistDeviceExtractorMOS3Transistor *make_mos3_extractor (const std::string &name) +static db::NetlistDeviceExtractorMOS3Transistor *make_mos3_extractor (const std::string &name, bool strict) { - return new db::NetlistDeviceExtractorMOS3Transistor (name); + return new db::NetlistDeviceExtractorMOS3Transistor (name, strict); } Class decl_NetlistDeviceExtractorMOS3Transistor (decl_dbNetlistDeviceExtractor, "db", "DeviceExtractorMOS3Transistor", - gsi::constructor ("new", &make_mos3_extractor, gsi::arg ("name"), - "@brief Creates a new device extractor with the given name." + gsi::constructor ("new", &make_mos3_extractor, gsi::arg ("name"), gsi::arg ("strict", false), + "@brief Creates a new device extractor with the given name.\n" + "If \\strict is true, the MOS device extraction will happen in strict mode. That is, source and drain " + "are not interchangeable." + ) + + gsi::method ("strict?", &db::NetlistDeviceExtractorMOS3Transistor::is_strict, + "@brief Returns a value indicating whether extraction happens in strict mode." ), "@brief A device extractor for a three-terminal MOS transistor\n" "\n" @@ -418,7 +423,8 @@ Class decl_NetlistDeviceExtractorMOS3T "The device class produced by this extractor is \\DeviceClassMOS3Transistor.\n" "The extractor extracts the six parameters of this class: L, W, AS, AD, PS and PD.\n" "\n" - "The device recognition layer names are 'SD' (source/drain) and 'G' (gate).\n" + "In strict mode, the device recognition layer names are 'S' (source), 'D' (drain) and 'G' (gate).\n" + "Otherwise, they are 'SD' (source/drain) and 'G' (gate).\n" "The terminal output layer names are 'tS' (source), 'tG' (gate) and 'tD' (drain).\n" "\n" "The diffusion area is distributed on the number of gates connecting to\n" @@ -430,13 +436,13 @@ Class decl_NetlistDeviceExtractorMOS3T "This class has been introduced in version 0.26." ); -db::NetlistDeviceExtractorMOS4Transistor *make_mos4_extractor (const std::string &name) +static db::NetlistDeviceExtractorMOS4Transistor *make_mos4_extractor (const std::string &name, bool strict) { - return new db::NetlistDeviceExtractorMOS4Transistor (name); + return new db::NetlistDeviceExtractorMOS4Transistor (name, strict); } Class decl_NetlistDeviceExtractorMOS4Transistor (decl_dbNetlistDeviceExtractor, "db", "DeviceExtractorMOS4Transistor", - gsi::constructor ("new", &make_mos4_extractor, gsi::arg ("name"), + gsi::constructor ("new", &make_mos4_extractor, gsi::arg ("name"), gsi::arg ("strict", false), "@brief Creates a new device extractor with the given name." ), "@brief A device extractor for a four-terminal MOS transistor\n" diff --git a/src/db/unit_tests/dbLayoutToNetlistReaderTests.cc b/src/db/unit_tests/dbLayoutToNetlistReaderTests.cc index 1b7bb5b4c..5f637911d 100644 --- a/src/db/unit_tests/dbLayoutToNetlistReaderTests.cc +++ b/src/db/unit_tests/dbLayoutToNetlistReaderTests.cc @@ -270,7 +270,7 @@ TEST(2_ReaderWithGlobalNets) { db::LayoutToNetlist l2n; - std::string in_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au_2.txt"); + std::string in_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_reader_au.txt"); tl::InputStream is_in (in_path); db::LayoutToNetlistStandardReader reader (is_in); @@ -285,7 +285,7 @@ TEST(2_ReaderWithGlobalNets) writer.write (&l2n); } - std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au_2.txt"); + std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_reader_au.txt"); compare_text_files (path, au_path); @@ -317,7 +317,7 @@ TEST(2_ReaderWithGlobalNets) std::string au = tl::testsrc (); au = tl::combine_path (au, "testdata"); au = tl::combine_path (au, "algo"); - au = tl::combine_path (au, "l2n_reader_au_2.gds"); + au = tl::combine_path (au, "l2n_reader_au_2r.gds"); db::compare_layouts (_this, ly2, au); } @@ -327,7 +327,7 @@ TEST(3_ReaderAbsoluteCoordinates) { db::LayoutToNetlist l2n; - std::string in_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au_2_abs.txt"); + std::string in_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_reader_au_abs.txt"); tl::InputStream is_in (in_path); db::LayoutToNetlistStandardReader reader (is_in); @@ -342,7 +342,7 @@ TEST(3_ReaderAbsoluteCoordinates) writer.write (&l2n); } - std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au_2.txt"); + std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_reader_au.txt"); compare_text_files (path, au_path); @@ -374,7 +374,7 @@ TEST(3_ReaderAbsoluteCoordinates) std::string au = tl::testsrc (); au = tl::combine_path (au, "testdata"); au = tl::combine_path (au, "algo"); - au = tl::combine_path (au, "l2n_reader_au_2.gds"); + au = tl::combine_path (au, "l2n_reader_au_2r.gds"); db::compare_layouts (_this, ly2, au); } diff --git a/src/db/unit_tests/dbLayoutToNetlistTests.cc b/src/db/unit_tests/dbLayoutToNetlistTests.cc index 640552385..c4b7ca373 100644 --- a/src/db/unit_tests/dbLayoutToNetlistTests.cc +++ b/src/db/unit_tests/dbLayoutToNetlistTests.cc @@ -554,15 +554,15 @@ TEST(1_BasicExtraction) db::compare_netlist (_this, *l2n.netlist (), "circuit RINGO (FB=FB,OSC=OSC,VSS=VSS,VDD=VDD);\n" " subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);\n" - " subcircuit INV2 $2 (IN=FB,$2=(null),OUT=$I19,$4=VSS,$5=VDD);\n" - " subcircuit INV2 $3 (IN=$I19,$2=(null),OUT=$I1,$4=VSS,$5=VDD);\n" - " subcircuit INV2 $4 (IN=$I1,$2=(null),OUT=$I2,$4=VSS,$5=VDD);\n" - " subcircuit INV2 $5 (IN=$I2,$2=(null),OUT=$I3,$4=VSS,$5=VDD);\n" - " subcircuit INV2 $6 (IN=$I3,$2=(null),OUT=$I4,$4=VSS,$5=VDD);\n" - " subcircuit INV2 $7 (IN=$I4,$2=(null),OUT=$I5,$4=VSS,$5=VDD);\n" - " subcircuit INV2 $8 (IN=$I5,$2=(null),OUT=$I6,$4=VSS,$5=VDD);\n" - " subcircuit INV2 $9 (IN=$I6,$2=(null),OUT=$I7,$4=VSS,$5=VDD);\n" - " subcircuit INV2 $10 (IN=$I7,$2=(null),OUT=$I8,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);\n" "end;\n" "circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n" " device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" @@ -583,7 +583,7 @@ TEST(1_BasicExtraction) // the transistor which supplies this probe target has been optimized away by "purge". EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (5.3, 0.0))), "(null)"); - EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (2.6, 1.0))), "INV2:$2"); + EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (2.6, 1.0))), "RINGO:$I39"); EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (6.4, 1.0))), "RINGO:$I2"); } @@ -806,14 +806,14 @@ TEST(2_Probing) db::compare_netlist (_this, *l2n.netlist (), "circuit RINGO (FB=FB,OSC=OSC,VSS=VSS,VDD=VDD);\n" " subcircuit INV2PAIR $1 ($1=FB,$2=VDD,$3=VSS,$4=$I3,$5=OSC);\n" - " subcircuit INV2PAIR $2 ($1=(null),$2=VDD,$3=VSS,$4=FB,$5=$I9);\n" - " subcircuit INV2PAIR $3 ($1=(null),$2=VDD,$3=VSS,$4=$I9,$5=$I1);\n" - " subcircuit INV2PAIR $4 ($1=(null),$2=VDD,$3=VSS,$4=$I1,$5=$I2);\n" - " subcircuit INV2PAIR $5 ($1=(null),$2=VDD,$3=VSS,$4=$I2,$5=$I3);\n" + " subcircuit INV2PAIR $2 ($1=$I18,$2=VDD,$3=VSS,$4=FB,$5=$I9);\n" + " subcircuit INV2PAIR $3 ($1=$I19,$2=VDD,$3=VSS,$4=$I9,$5=$I1);\n" + " subcircuit INV2PAIR $4 ($1=$I20,$2=VDD,$3=VSS,$4=$I1,$5=$I2);\n" + " subcircuit INV2PAIR $5 ($1=$I21,$2=VDD,$3=VSS,$4=$I2,$5=$I3);\n" "end;\n" "circuit INV2PAIR ($1=$I7,$2=$I5,$3=$I4,$4=$I2,$5=$I1);\n" " subcircuit INV2 $1 (IN=$I3,$2=$I7,OUT=$I1,$4=$I4,$5=$I5);\n" - " subcircuit INV2 $2 (IN=$I2,$2=(null),OUT=$I3,$4=$I4,$5=$I5);\n" + " subcircuit INV2 $2 (IN=$I2,$2=$I6,OUT=$I3,$4=$I4,$5=$I5);\n" "end;\n" "circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n" " device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" @@ -834,7 +834,7 @@ TEST(2_Probing) // the transistor which supplies this probe target has been optimized away by "purge". EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (5.3, 0.0))), "(null)"); - EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (2.6, 1.0))), "INV2PAIR:$I7"); + EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (2.6, 1.0))), "RINGO:$I18"); EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (6.4, 1.0))), "INV2PAIR:$I3"); } @@ -1087,13 +1087,13 @@ TEST(3_GlobalNetConnections) db::compare_netlist (_this, *l2n.netlist (), "circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);\n" " subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I7,$6=OSC,$7=VDD);\n" - " subcircuit INV2PAIR $2 (BULK=VSS,$2=(null),$3=VDD,$4=VSS,$5=FB,$6=$I13,$7=VDD);\n" - " subcircuit INV2PAIR $3 (BULK=VSS,$2=(null),$3=VDD,$4=VSS,$5=$I13,$6=$I5,$7=VDD);\n" - " subcircuit INV2PAIR $4 (BULK=VSS,$2=(null),$3=VDD,$4=VSS,$5=$I5,$6=$I6,$7=VDD);\n" - " subcircuit INV2PAIR $5 (BULK=VSS,$2=(null),$3=VDD,$4=VSS,$5=$I6,$6=$I7,$7=VDD);\n" + " subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I13,$7=VDD);\n" + " subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I13,$6=$I5,$7=VDD);\n" + " subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I5,$6=$I6,$7=VDD);\n" + " subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I6,$6=$I7,$7=VDD);\n" "end;\n" "circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);\n" - " subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=(null),OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);\n" + " subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);\n" " subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);\n" "end;\n" "circuit INV2 ($1=(null),IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=(null));\n" @@ -1115,7 +1115,7 @@ TEST(3_GlobalNetConnections) // the transistor which supplies this probe target has been optimized away by "purge". EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (5.3, 0.0))), "(null)"); - EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (2.6, 1.0))), "INV2PAIR:$I8"); + EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (2.6, 1.0))), "RINGO:$I22"); EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (6.4, 1.0))), "INV2PAIR:$I4"); } @@ -1374,13 +1374,13 @@ TEST(4_GlobalNetDeviceExtraction) db::compare_netlist (_this, *l2n.netlist (), "circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);\n" " subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I7,$6=OSC,$7=VDD);\n" - " subcircuit INV2PAIR $2 (BULK=VSS,$2=(null),$3=VDD,$4=VSS,$5=FB,$6=$I13,$7=VDD);\n" - " subcircuit INV2PAIR $3 (BULK=VSS,$2=(null),$3=VDD,$4=VSS,$5=$I13,$6=$I5,$7=VDD);\n" - " subcircuit INV2PAIR $4 (BULK=VSS,$2=(null),$3=VDD,$4=VSS,$5=$I5,$6=$I6,$7=VDD);\n" - " subcircuit INV2PAIR $5 (BULK=VSS,$2=(null),$3=VDD,$4=VSS,$5=$I6,$6=$I7,$7=VDD);\n" + " subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I13,$7=VDD);\n" + " subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I13,$6=$I5,$7=VDD);\n" + " subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I5,$6=$I6,$7=VDD);\n" + " subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I6,$6=$I7,$7=VDD);\n" "end;\n" "circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);\n" - " subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=(null),OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);\n" + " subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);\n" " subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);\n" "end;\n" "circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);\n" @@ -1402,7 +1402,7 @@ TEST(4_GlobalNetDeviceExtraction) // the transistor which supplies this probe target has been optimized away by "purge". EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (5.3, 0.0))), "(null)"); - EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (2.6, 1.0))), "INV2PAIR:$I8"); + EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (2.6, 1.0))), "RINGO:$I22"); EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (6.4, 1.0))), "INV2PAIR:$I4"); } @@ -1658,10 +1658,10 @@ TEST(5_DeviceExtractionWithDeviceCombination) db::compare_netlist (_this, *l2n.netlist (), "circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);\n" " subcircuit INV2PAIR $1 (BULK=VSS,$2=VDD,$3=VSS,$4=FB,$5=$I7,$6=OSC,$7=VDD);\n" - " subcircuit INV2PAIR $2 (BULK=VSS,$2=VDD,$3=VSS,$4=(null),$5=FB,$6=$I13,$7=VDD);\n" - " subcircuit INV2PAIR $3 (BULK=VSS,$2=VDD,$3=VSS,$4=(null),$5=$I13,$6=$I5,$7=VDD);\n" - " subcircuit INV2PAIR $4 (BULK=VSS,$2=VDD,$3=VSS,$4=(null),$5=$I5,$6=$I6,$7=VDD);\n" - " subcircuit INV2PAIR $5 (BULK=VSS,$2=VDD,$3=VSS,$4=(null),$5=$I6,$6=$I7,$7=VDD);\n" + " subcircuit INV2PAIR $2 (BULK=VSS,$2=VDD,$3=VSS,$4=$I22,$5=FB,$6=$I13,$7=VDD);\n" + " subcircuit INV2PAIR $3 (BULK=VSS,$2=VDD,$3=VSS,$4=$I23,$5=$I13,$6=$I5,$7=VDD);\n" + " subcircuit INV2PAIR $4 (BULK=VSS,$2=VDD,$3=VSS,$4=$I24,$5=$I5,$6=$I6,$7=VDD);\n" + " subcircuit INV2PAIR $5 (BULK=VSS,$2=VDD,$3=VSS,$4=$I25,$5=$I6,$6=$I7,$7=VDD);\n" "end;\n" "circuit INV2PAIR (BULK=BULK,$2=$I6,$3=$I5,$4=$I4,$5=$I3,$6=$I2,$7=$I1);\n" " subcircuit INV2 $1 ($1=$I1,IN=$I3,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);\n" diff --git a/src/db/unit_tests/dbLayoutToNetlistWriterTests.cc b/src/db/unit_tests/dbLayoutToNetlistWriterTests.cc index f2f12169e..2db34248d 100644 --- a/src/db/unit_tests/dbLayoutToNetlistWriterTests.cc +++ b/src/db/unit_tests/dbLayoutToNetlistWriterTests.cc @@ -371,14 +371,14 @@ TEST(2_WriterWithGlobalNets) l2n.netlist ()->make_top_level_pins (); l2n.netlist ()->purge (); - std::string path = tmp_file ("tmp_l2nwriter_2.txt"); + std::string path = tmp_file ("tmp_l2nwriter_2b.txt"); { tl::OutputStream stream (path); db::LayoutToNetlistStandardWriter writer (stream, false); writer.write (&l2n); } - std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au_2.txt"); + std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au_2b.txt"); compare_text_files (path, au_path); diff --git a/src/db/unit_tests/dbNetlistCompareTests.cc b/src/db/unit_tests/dbNetlistCompareTests.cc index 60267320e..7d2443e95 100644 --- a/src/db/unit_tests/dbNetlistCompareTests.cc +++ b/src/db/unit_tests/dbNetlistCompareTests.cc @@ -1661,6 +1661,7 @@ TEST(11_MismatchingSubcircuits) NetlistCompareTestLogger logger; db::NetlistComparer comp (&logger); + comp.set_dont_consider_net_names (true); bool good = comp.compare (&nl1, &nl2); @@ -1696,6 +1697,7 @@ TEST(11_MismatchingSubcircuits) db::NetlistCrossReference xref; db::NetlistComparer comp_xref (&xref); + comp_xref.set_dont_consider_net_names (true); good = comp_xref.compare (&nl1, &nl2); @@ -2053,12 +2055,12 @@ TEST(14_Subcircuit2NandMismatchNoSwap) "net_mismatch INT IN1\n" "net_mismatch IN1 INT\n" "net_mismatch IN2 IN2\n" - "pin_mismatch $0 (null)\n" + "match_pins $0 (null)\n" "match_pins $1 $1\n" "match_pins $2 $2\n" "match_pins $3 $3\n" "match_pins $4 $4\n" - "pin_mismatch (null) $0\n" + "match_pins (null) $0\n" "match_subcircuits $2 $1\n" "subcircuit_mismatch $1 $2\n" "end_circuit TOP TOP NOMATCH" @@ -2106,8 +2108,8 @@ TEST(14_Subcircuit2NandMismatchNoSwap) " device $1:$1 [Match]\n" " device $2:$2 [Match]\n" "TOP:TOP [NoMatch]:\n" - " pin (null):$0 [Mismatch]\n" - " pin $0:(null) [Mismatch]\n" + " pin (null):$0 [Match]\n" + " pin $0:(null) [Match]\n" " pin $1:$1 [Match]\n" " pin $2:$2 [Match]\n" " pin $3:$3 [Match]\n" @@ -2521,6 +2523,7 @@ TEST(17_InherentlyAmbiguousDecoder) NetlistCompareTestLogger logger; db::NetlistComparer comp (&logger); comp.equivalent_pins (nl2.circuit_by_name ("NAND"), 0, 1); + comp.set_dont_consider_net_names (true); bool good = comp.compare (&nl1, &nl2); @@ -2572,7 +2575,61 @@ TEST(17_InherentlyAmbiguousDecoder) EXPECT_EQ (good, true); + comp.set_dont_consider_net_names (false); + logger.clear (); + good = comp.compare (&nl1, &nl2); + + EXPECT_EQ (logger.text (), + "begin_circuit NAND NAND\n" + "match_nets VSS VSS\n" + "match_nets INT INT\n" + "match_nets OUT OUT\n" + "match_nets VDD VDD\n" + "match_nets B B\n" + "match_nets A A\n" + "match_pins $0 $0\n" + "match_pins $1 $1\n" + "match_pins $2 $2\n" + "match_pins $3 $3\n" + "match_pins $4 $4\n" + "match_devices $1 $1\n" + "match_devices $2 $2\n" + "match_devices $3 $3\n" + "match_devices $4 $4\n" + "end_circuit NAND NAND MATCH\n" + "begin_circuit DECODER DECODER\n" + "match_nets VSS VSS\n" + "match_nets VDD VDD\n" + "match_nets NQ0 NQ0\n" + "match_nets NQ1 NQ1\n" + "match_nets NQ2 NQ2\n" + "match_nets NQ3 NQ3\n" + "match_ambiguous_nets NA NA\n" + "match_ambiguous_nets NB NB\n" + "match_nets B B\n" + "match_nets A A\n" + "match_pins $0 $1\n" + "match_pins $1 $0\n" + "match_pins $2 $2\n" + "match_pins $3 $3\n" + "match_pins $4 $4\n" + "match_pins $5 $5\n" + "match_pins $6 $6\n" + "match_pins $7 $7\n" + "match_subcircuits $1 $1\n" + "match_subcircuits $2 $2\n" + "match_subcircuits $4 $3\n" + "match_subcircuits $6 $4\n" + "match_subcircuits $3 $5\n" + "match_subcircuits $5 $6\n" + "end_circuit DECODER DECODER MATCH" + ); + + EXPECT_EQ (good, true); + + logger.clear (); + comp.set_dont_consider_net_names (true); comp.same_nets (nl1.circuit_by_name ("DECODER")->net_by_name ("A"), nl2.circuit_by_name ("DECODER")->net_by_name ("A")); good = comp.compare (&nl1, &nl2); diff --git a/src/db/unit_tests/dbNetlistExtractorTests.cc b/src/db/unit_tests/dbNetlistExtractorTests.cc index e841c2cb8..932334032 100644 --- a/src/db/unit_tests/dbNetlistExtractorTests.cc +++ b/src/db/unit_tests/dbNetlistExtractorTests.cc @@ -36,6 +36,7 @@ #include "dbTestSupport.h" #include "dbCellMapping.h" #include "dbTestSupport.h" +#include "dbNetlistCompare.h" #include "tlUnitTest.h" #include "tlString.h" @@ -353,15 +354,15 @@ TEST(1_DeviceAndNetExtraction) db::compare_netlist (_this, nl, "circuit RINGO (FB=FB,OSC=OSC,VSS=VSS,VDD=VDD);\n" " subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);\n" - " subcircuit INV2 $2 (IN=FB,$2=(null),OUT=$I19,$4=VSS,$5=VDD);\n" - " subcircuit INV2 $3 (IN=$I19,$2=(null),OUT=$I1,$4=VSS,$5=VDD);\n" - " subcircuit INV2 $4 (IN=$I1,$2=(null),OUT=$I2,$4=VSS,$5=VDD);\n" - " subcircuit INV2 $5 (IN=$I2,$2=(null),OUT=$I3,$4=VSS,$5=VDD);\n" - " subcircuit INV2 $6 (IN=$I3,$2=(null),OUT=$I4,$4=VSS,$5=VDD);\n" - " subcircuit INV2 $7 (IN=$I4,$2=(null),OUT=$I5,$4=VSS,$5=VDD);\n" - " subcircuit INV2 $8 (IN=$I5,$2=(null),OUT=$I6,$4=VSS,$5=VDD);\n" - " subcircuit INV2 $9 (IN=$I6,$2=(null),OUT=$I7,$4=VSS,$5=VDD);\n" - " subcircuit INV2 $10 (IN=$I7,$2=(null),OUT=$I8,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);\n" "end;\n" "circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n" " device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" @@ -818,15 +819,15 @@ TEST(3_DeviceAndNetExtractionWithImplicitConnections) db::compare_netlist (_this, nl, "circuit RINGO (FB=FB,OSC=OSC,NEXT=NEXT,'VSSZ,VSS'='VSSZ,VSS','VDDZ,VDD'='VDDZ,VDD');\n" " subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" - " subcircuit INV2 $2 (IN=FB,$2=(null),OUT=$I19,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" - " subcircuit INV2 $3 (IN=NEXT,$2=(null),OUT=$I5,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" - " subcircuit INV2 $4 (IN=$I3,$2=(null),OUT=NEXT,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" - " subcircuit INV2 $5 (IN=$I5,$2=(null),OUT=$I6,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" - " subcircuit INV2 $6 (IN=$I6,$2=(null),OUT=$I7,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" - " subcircuit INV2 $7 (IN=$I7,$2=(null),OUT=$I8,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" - " subcircuit INV2 $8 (IN=$I19,$2=(null),OUT=$I1,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" - " subcircuit INV2 $9 (IN=$I1,$2=(null),OUT=$I2,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" - " subcircuit INV2 $10 (IN=$I2,$2=(null),OUT=$I3,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $3 (IN=NEXT,$2=$I43,OUT=$I5,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $4 (IN=$I3,$2=$I42,OUT=NEXT,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $5 (IN=$I5,$2=$I44,OUT=$I6,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $6 (IN=$I6,$2=$I45,OUT=$I7,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $7 (IN=$I7,$2=$I46,OUT=$I8,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $8 (IN=$I19,$2=$I39,OUT=$I1,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $9 (IN=$I1,$2=$I40,OUT=$I2,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $10 (IN=$I2,$2=$I41,OUT=$I3,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" "end;\n" "circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n" " device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" @@ -1864,3 +1865,246 @@ TEST(8_DiodeExtractionScaled) db::compare_layouts (_this, ly, au); } + +TEST(9_StrictDeviceExtraction) +{ + db::Layout ly; + db::LayerMap lmap; + + unsigned int nwell = define_layer (ly, lmap, 1); + unsigned int active = define_layer (ly, lmap, 2); + unsigned int poly = define_layer (ly, lmap, 3); + unsigned int poly_lbl = define_layer (ly, lmap, 3, 1); + unsigned int diff_cont = define_layer (ly, lmap, 4); + unsigned int poly_cont = define_layer (ly, lmap, 5); + unsigned int metal1 = define_layer (ly, lmap, 6); + unsigned int metal1_lbl = define_layer (ly, lmap, 6, 1); + unsigned int via1 = define_layer (ly, lmap, 7); + unsigned int metal2 = define_layer (ly, lmap, 8); + unsigned int metal2_lbl = define_layer (ly, lmap, 8, 1); + unsigned int source = define_layer (ly, lmap, 10); + + { + db::LoadLayoutOptions options; + options.get_options ().layer_map = lmap; + options.get_options ().create_other_layers = false; + + std::string fn (tl::testsrc ()); + fn = tl::combine_path (fn, "testdata"); + fn = tl::combine_path (fn, "algo"); + fn = tl::combine_path (fn, "device_extract_l9.gds"); + + tl::InputStream stream (fn); + db::Reader reader (stream); + reader.read (ly, options); + } + + db::Cell &tc = ly.cell (*ly.begin_top_down ()); + + db::DeepShapeStore dss; + dss.set_text_enlargement (1); + dss.set_text_property_name (tl::Variant ("LABEL")); + + // original layers + db::Region rnwell (db::RecursiveShapeIterator (ly, tc, nwell), dss); + db::Region ractive (db::RecursiveShapeIterator (ly, tc, active), dss); + db::Region rpoly (db::RecursiveShapeIterator (ly, tc, poly), dss); + db::Region rpoly_lbl (db::RecursiveShapeIterator (ly, tc, poly_lbl), dss); + db::Region rdiff_cont (db::RecursiveShapeIterator (ly, tc, diff_cont), dss); + db::Region rpoly_cont (db::RecursiveShapeIterator (ly, tc, poly_cont), dss); + db::Region rmetal1 (db::RecursiveShapeIterator (ly, tc, metal1), dss); + db::Region rmetal1_lbl (db::RecursiveShapeIterator (ly, tc, metal1_lbl), dss); + db::Region rvia1 (db::RecursiveShapeIterator (ly, tc, via1), dss); + db::Region rmetal2 (db::RecursiveShapeIterator (ly, tc, metal2), dss); + db::Region rmetal2_lbl (db::RecursiveShapeIterator (ly, tc, metal2_lbl), dss); + db::Region rsource (db::RecursiveShapeIterator (ly, tc, source), dss); + + // derived regions + + db::Region rpactive = ractive & rnwell; + db::Region rpgate = rpactive & rpoly; + db::Region rpsd = rpactive - rpgate; + db::Region rps = rpsd & rsource; + db::Region rpd = rpsd - rsource; + + db::Region rnactive = ractive - rnwell; + db::Region rngate = rnactive & rpoly; + db::Region rnsd = rnactive - rngate; + db::Region rns = rnsd & rsource; + db::Region rnd = rnsd - rsource; + + // return the computed layers into the original layout and write it for debugging purposes + + unsigned int lgate = ly.insert_layer (db::LayerProperties (20, 0)); // 10/0 -> Gate + unsigned int lsd = ly.insert_layer (db::LayerProperties (21, 0)); // 11/0 -> Source/Drain + unsigned int lpdiff = ly.insert_layer (db::LayerProperties (22, 0)); // 12/0 -> P Diffusion + unsigned int lndiff = ly.insert_layer (db::LayerProperties (23, 0)); // 13/0 -> N Diffusion + + rpgate.insert_into (&ly, tc.cell_index (), lgate); + rngate.insert_into (&ly, tc.cell_index (), lgate); + rps.insert_into (&ly, tc.cell_index (), lsd); + rpd.insert_into (&ly, tc.cell_index (), lsd); + rns.insert_into (&ly, tc.cell_index (), lsd); + rnd.insert_into (&ly, tc.cell_index (), lsd); + rpsd.insert_into (&ly, tc.cell_index (), lpdiff); + rnsd.insert_into (&ly, tc.cell_index (), lndiff); + + // perform the extraction + + db::Netlist nl; + db::hier_clusters cl; + + db::NetlistDeviceExtractorMOS3Transistor pmos_ex ("PMOS", true /*strict*/); + db::NetlistDeviceExtractorMOS3Transistor nmos_ex ("NMOS", true /*strict*/); + + db::NetlistDeviceExtractor::input_layers dl; + + dl["S"] = &rps; + dl["D"] = &rpd; + dl["G"] = &rpgate; + dl["P"] = &rpoly; // not needed for extraction but to return terminal shapes + pmos_ex.extract (dss, 0, dl, nl, cl); + + dl["S"] = &rns; + dl["D"] = &rnd; + dl["G"] = &rngate; + dl["P"] = &rpoly; // not needed for extraction but to return terminal shapes + nmos_ex.extract (dss, 0, dl, nl, cl); + + // perform the net extraction + + db::NetlistExtractor net_ex; + + db::Connectivity conn; + // Intra-layer + conn.connect (rps); + conn.connect (rpd); + conn.connect (rns); + conn.connect (rnd); + conn.connect (rpoly); + conn.connect (rdiff_cont); + conn.connect (rpoly_cont); + conn.connect (rmetal1); + conn.connect (rvia1); + conn.connect (rmetal2); + // Inter-layer + conn.connect (rps, rdiff_cont); + conn.connect (rpd, rdiff_cont); + conn.connect (rns, rdiff_cont); + conn.connect (rnd, rdiff_cont); + conn.connect (rpoly, rpoly_cont); + conn.connect (rpoly_cont, rmetal1); + conn.connect (rdiff_cont, rmetal1); + conn.connect (rmetal1, rvia1); + conn.connect (rvia1, rmetal2); + conn.connect (rpoly, rpoly_lbl); // attaches labels + conn.connect (rmetal1, rmetal1_lbl); // attaches labels + conn.connect (rmetal2, rmetal2_lbl); // attaches labels + + // extract the nets + + net_ex.extract_nets (dss, 0, conn, nl, cl); + + // debug layers produced for nets + // 202/0 -> Active + // 203/0 -> Poly + // 204/0 -> Diffusion contacts + // 205/0 -> Poly contacts + // 206/0 -> Metal1 + // 207/0 -> Via1 + // 208/0 -> Metal2 + // 210/0 -> N source/drain + // 211/0 -> P source/drain + std::map dump_map; + dump_map [layer_of (rps) ] = ly.insert_layer (db::LayerProperties (210, 0)); + dump_map [layer_of (rpd) ] = ly.insert_layer (db::LayerProperties (211, 0)); + dump_map [layer_of (rns) ] = ly.insert_layer (db::LayerProperties (212, 0)); + dump_map [layer_of (rnd) ] = ly.insert_layer (db::LayerProperties (213, 0)); + dump_map [layer_of (rpoly) ] = ly.insert_layer (db::LayerProperties (203, 0)); + dump_map [layer_of (rdiff_cont)] = ly.insert_layer (db::LayerProperties (204, 0)); + dump_map [layer_of (rpoly_cont)] = ly.insert_layer (db::LayerProperties (205, 0)); + dump_map [layer_of (rmetal1) ] = ly.insert_layer (db::LayerProperties (206, 0)); + dump_map [layer_of (rvia1) ] = ly.insert_layer (db::LayerProperties (207, 0)); + dump_map [layer_of (rmetal2) ] = ly.insert_layer (db::LayerProperties (208, 0)); + + // write nets to layout + db::CellMapping cm = dss.cell_mapping_to_original (0, &ly, tc.cell_index ()); + dump_nets_to_layout (nl, cl, ly, dump_map, cm); + + std::string nl_au_string = + "circuit RINGO ();\n" + " subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);\n" + "end;\n" + "circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n" + " device PMOS $1 (S=$5,G=IN,D=$2) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $2 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $3 (S=$4,G=IN,D=$2) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $4 (S=$4,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " subcircuit TRANS $1 ($1=$2,$2=$4,$3=IN);\n" + " subcircuit TRANS $2 ($1=$2,$2=$5,$3=IN);\n" + " subcircuit TRANS $3 ($1=$5,$2=OUT,$3=$2);\n" + " subcircuit TRANS $4 ($1=$4,$2=OUT,$3=$2);\n" + "end;\n" + "circuit TRANS ($1=$1,$2=$2,$3=$3);\n" + "end;\n"; + + // compare netlist as string + CHECKPOINT (); + db::compare_netlist (_this, nl, nl_au_string); + + { + // compare vs. non-strict device classes + db::Netlist au_nl; + // non-strict + db::DeviceClass *dc; + dc = new db::DeviceClassMOS3Transistor (); + dc->set_name ("PMOS"); + au_nl.add_device_class (dc); + dc = new db::DeviceClassMOS3Transistor (); + dc->set_name ("NMOS"); + au_nl.add_device_class (dc); + au_nl.from_string (nl_au_string); + + CHECKPOINT (); + db::compare_netlist (_this, nl, au_nl); + } + + { + std::string nl_au_string_wrong_terminals = nl_au_string; + nl_au_string_wrong_terminals = tl::replaced (nl_au_string_wrong_terminals, "(S=$5,G=IN,D=$2)", "(S=$2,G=IN,D=$5)"); + nl_au_string_wrong_terminals = tl::replaced (nl_au_string_wrong_terminals, "(S=$4,G=IN,D=$2)", "(S=$2,G=IN,D=$4)"); + + // compare vs. non-strict device classes with WRONG terminal assignment + db::Netlist au_nl; + // non-strict + db::DeviceClass *dc; + dc = new db::DeviceClassMOS3Transistor (); + dc->set_name ("PMOS"); + au_nl.add_device_class (dc); + dc = new db::DeviceClassMOS3Transistor (); + dc->set_name ("NMOS"); + au_nl.add_device_class (dc); + au_nl.from_string (nl_au_string_wrong_terminals); + + db::NetlistComparer comp (0); + EXPECT_EQ (comp.compare (&nl, &au_nl), false); + } + + // compare the collected test data + + std::string au = tl::testsrc (); + au = tl::combine_path (au, "testdata"); + au = tl::combine_path (au, "algo"); + au = tl::combine_path (au, "device_extract_au9.gds"); + + db::compare_layouts (_this, ly, au); +} diff --git a/src/db/unit_tests/dbNetlistReaderTests.cc b/src/db/unit_tests/dbNetlistReaderTests.cc index c39e477a6..98a6b3491 100644 --- a/src/db/unit_tests/dbNetlistReaderTests.cc +++ b/src/db/unit_tests/dbNetlistReaderTests.cc @@ -137,10 +137,10 @@ TEST(4_ReaderWithUnconnectedPins) EXPECT_EQ (nl.to_string (), "circuit RINGO ('1'='1','2'='2','3'='3','4'='4');\n" " subcircuit INV2PAIR $1 ('1'='4','2'='3','3'='4','4'='1','5'='6','6'='2','7'='3');\n" - " subcircuit INV2PAIR $2 ('1'='4','2'='3','3'='4','4'=(null),'5'='1','6'='5','7'='3');\n" - " subcircuit INV2PAIR $3 ('1'='4','2'='3','3'='4','4'=(null),'5'='5','6'='8','7'='3');\n" - " subcircuit INV2PAIR $4 ('1'='4','2'='3','3'='4','4'=(null),'5'='8','6'='7','7'='3');\n" - " subcircuit INV2PAIR $5 ('1'='4','2'='3','3'='4','4'=(null),'5'='7','6'='6','7'='3');\n" + " subcircuit INV2PAIR $2 ('1'='4','2'='3','3'='4','4'='100','5'='1','6'='5','7'='3');\n" + " subcircuit INV2PAIR $3 ('1'='4','2'='3','3'='4','4'='101','5'='5','6'='8','7'='3');\n" + " subcircuit INV2PAIR $4 ('1'='4','2'='3','3'='4','4'='102','5'='8','6'='7','7'='3');\n" + " subcircuit INV2PAIR $5 ('1'='4','2'='3','3'='4','4'='103','5'='7','6'='6','7'='3');\n" "end;\n" "circuit INV2PAIR ('1'='1','2'='2','3'='3','4'='4','5'='5','6'='6','7'='7');\n" " subcircuit INV2 $1 ('1'='7','2'='5','3'='4','4'='3','5'='2','6'='1');\n" @@ -251,7 +251,7 @@ TEST(6_ReaderWithDelegate) " device RES $1 (A=A,B=Z) (R=100000,L=0,W=0,A=0,P=0);\n" "end;\n" "circuit .TOP ();\n" - " subcircuit SUBCKT SUBCKT ($1=(null),A=(null),VDD=(null),Z=(null),GND=VSS,GND$1=VSS);\n" + " subcircuit SUBCKT SUBCKT ($1=IN,A=OUT,VDD=VDD,Z=Z,GND=VSS,GND$1=VSS);\n" "end;\n" ); } @@ -294,3 +294,93 @@ TEST(7_GlobalNets) "end;\n" ); } + +TEST(8_Include) +{ + db::Netlist nl; + + std::string path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "nreader8.cir"); + + db::NetlistSpiceReader reader; + tl::InputStream is (path); + reader.read (is, nl); + + EXPECT_EQ (nl.to_string (), + "circuit INVX1 ('1'='1','2'='2','3'='3','4'='4','5'='5','6'='6');\n" + " device MLVPMOS $1 (S='1',G='5',D='2',B='4') (L=0.25,W=1.5,AS=0,AD=0,PS=0,PD=0);\n" + " device MLVNMOS $2 (S='3',G='5',D='2',B='6') (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);\n" + "end;\n" + "circuit ND2X1 ('1'='1','2'='2','3'='3','4'='4','5'='5','6'='6','7'='7');\n" + " device MLVPMOS $1 (S='2',G='6',D='1',B='4') (L=0.25,W=1.5,AS=0,AD=0,PS=0,PD=0);\n" + " device MLVPMOS $2 (S='1',G='5',D='2',B='4') (L=0.25,W=1.5,AS=0,AD=0,PS=0,PD=0);\n" + " device MLVNMOS $3 (S='3',G='6',D='8',B='7') (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);\n" + " device MLVNMOS $4 (S='8',G='5',D='2',B='7') (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);\n" + "end;\n" + "circuit RINGO ('11'='11','12'='12','13'='13','14'='14','15'='15');\n" + " subcircuit ND2X1 $1 ('1'='12','2'='1','3'='15','4'='12','5'='11','6'='14','7'='15');\n" + " subcircuit INVX1 $2 ('1'='12','2'='2','3'='15','4'='12','5'='1','6'='15');\n" + " subcircuit INVX1 $3 ('1'='12','2'='3','3'='15','4'='12','5'='2','6'='15');\n" + " subcircuit INVX1 $4 ('1'='12','2'='4','3'='15','4'='12','5'='3','6'='15');\n" + " subcircuit INVX1 $5 ('1'='12','2'='5','3'='15','4'='12','5'='4','6'='15');\n" + " subcircuit INVX1 $6 ('1'='12','2'='6','3'='15','4'='12','5'='5','6'='15');\n" + " subcircuit INVX1 $7 ('1'='12','2'='7','3'='15','4'='12','5'='6','6'='15');\n" + " subcircuit INVX1 $8 ('1'='12','2'='8','3'='15','4'='12','5'='7','6'='15');\n" + " subcircuit INVX1 $9 ('1'='12','2'='9','3'='15','4'='12','5'='8','6'='15');\n" + " subcircuit INVX1 $10 ('1'='12','2'='10','3'='15','4'='12','5'='9','6'='15');\n" + " subcircuit INVX1 $11 ('1'='12','2'='11','3'='15','4'='12','5'='10','6'='15');\n" + " subcircuit INVX1 $12 ('1'='12','2'='13','3'='15','4'='12','5'='11','6'='15');\n" + "end;\n" + ); +} + +TEST(9_DeviceMultipliers) +{ + db::Netlist nl; + + std::string path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "nreader9.cir"); + + db::NetlistSpiceReader reader; + tl::InputStream is (path); + reader.read (is, nl); + + std::string nl_string = nl.to_string (); + // normalization of exponential representation: + nl_string = tl::replaced (nl_string, "e-009", "e-09"); + + EXPECT_EQ (nl_string, + "circuit .TOP ();\n" + " device RES $1 (A='1',B='2') (R=850,L=0,W=0,A=0,P=0);\n" + " device RES $2 (A='3',B='4') (R=1700,L=0,W=0,A=0,P=0);\n" + " device NMOS $1 (S='1',G='2',D='3',B='4') (L=7,W=4,AS=0,AD=0,PS=0,PD=0);\n" + " device PMOS $2 (S='1',G='2',D='3',B='4') (L=7,W=2,AS=0,AD=0,PS=0,PD=0);\n" + " device CAP $1 (A='1',B='2') (C=2e-09,A=0,P=0);\n" + " device CAP $2 (A='3',B='4') (C=1e-09,A=0,P=0);\n" + " device DIODE $1 (A='1',C='2') (A=20,P=0);\n" + " device DIODE $2 (A='3',C='4') (A=10,P=0);\n" + " device BIP $1 (C='1',B='2',E='3',S='4') (AE=20,PE=0,AB=0,PB=0,AC=0,PC=0,NE=1);\n" + " device BIP $2 (C='1',B='2',E='3',S='4') (AE=10,PE=0,AB=0,PB=0,AC=0,PC=0,NE=1);\n" + "end;\n" + ); +} + +TEST(10_SubcircuitsNoPins) +{ + db::Netlist nl; + + std::string path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "nreader10.cir"); + + db::NetlistSpiceReader reader; + tl::InputStream is (path); + reader.read (is, nl); + + EXPECT_EQ (nl.to_string (), + "circuit .TOP ();\n" + " device RES $1 (A=VDD,B=GND) (R=1000,L=0,W=0,A=0,P=0);\n" + " subcircuit FILLER_CAP '0' (VDD=VDD,GND=GND);\n" + "end;\n" + "circuit FILLER_CAP (VDD=VDD,GND=GND);\n" + " device NMOS '0' (S=GND,G=VDD,D=GND,B=GND) (L=10,W=10,AS=0,AD=0,PS=0,PD=0);\n" + "end;\n" + ); +} + diff --git a/src/db/unit_tests/dbNetlistTests.cc b/src/db/unit_tests/dbNetlistTests.cc index fdffed627..a4db90bb7 100644 --- a/src/db/unit_tests/dbNetlistTests.cc +++ b/src/db/unit_tests/dbNetlistTests.cc @@ -780,7 +780,7 @@ TEST(7_NetTerminalsEditing) EXPECT_EQ (n1->terminal_count (), size_t (1)); EXPECT_EQ (n1->pin_count (), size_t (0)); - EXPECT_EQ (n1->is_floating (), true); + EXPECT_EQ (n1->is_floating (), false); EXPECT_EQ (n1->is_internal (), false); d2->connect_terminal (1, n1); diff --git a/src/drc/drc/built-in-macros/_drc_engine.rb b/src/drc/drc/built-in-macros/_drc_engine.rb index 9ffaf7d79..f513aef6d 100644 --- a/src/drc/drc/built-in-macros/_drc_engine.rb +++ b/src/drc/drc/built-in-macros/_drc_engine.rb @@ -20,6 +20,9 @@ module DRC cv = RBA::CellView::active + @generator = "" + @rdb_index = nil + @l2ndb_index = nil @def_layout = cv && cv.layout @def_cell = cv && cv.cell @def_path = cv && cv.filename @@ -161,6 +164,32 @@ module DRC RBA::DeviceExtractorMOS4Transistor::new(name) end + # %DRC% + # @brief Supplies the DMOS3 transistor extractor class + # @name dmos3 + # @synopsis dmos3(name) + # Use this class with \extract_devices to specify extraction of a + # three-terminal DMOS transistor. A DMOS transistor is essentially + # the same than a MOS transistor, but source and drain are + # separated. + + def dmos3(name) + RBA::DeviceExtractorMOS3Transistor::new(name, true) + end + + # %DRC% + # @brief Supplies the MOS4 transistor extractor class + # @name dmos4 + # @synopsis dmos4(name) + # Use this class with \extract_devices to specify extraction of a + # four-terminal DMOS transistor. A DMOS transistor is essentially + # the same than a MOS transistor, but source and drain are + # separated. + + def dmos4(name) + RBA::DeviceExtractorMOS4Transistor::new(name, true) + end + # %DRC% # @brief Supplies the BJT3 transistor extractor class # @name bjt3 @@ -734,10 +763,17 @@ module DRC name = filename && File::basename(filename) name ||= "DRC" - lv = RBA::LayoutView::current - if lv - @output_rdb_index = lv.create_rdb(name) - @output_rdb = lv.rdb(@output_rdb_index) + @output_rdb_index = nil + + view = RBA::LayoutView::current + if view + if self._rdb_index + @output_rdb = RBA::ReportDatabase::new("") # reuse existing name + @output_rdb_index = view.replace_rdb(self._rdb_index, @output_rdb) + else + @output_rdb = RBA::ReportDatabase::new(name) + @output_rdb_index = view.add_rdb(@output_rdb) + end else @output_rdb = RBA::ReportDatabase::new(name) end @@ -754,7 +790,7 @@ module DRC cn || raise("No cell name specified - either the source was not specified before 'report' or there is no default source. In the latter case, specify a cell name as the third parameter of 'report'") @output_rdb_cell = @output_rdb.create_cell(cn) - @output_rdb.generator = $0 + @output_rdb.generator = self._generator @output_rdb.top_cell_name = cn @output_rdb.description = description @@ -1440,7 +1476,11 @@ CODE # NOTE: to prevent the netter destroying the database, we need to take it l2ndb = _take_data - l2ndb_index = view.add_l2ndb(l2ndb) + if self._l2ndb_index + l2ndb_index = view.replace_l2ndb(self._l2ndb_index, l2ndb) + else + l2ndb_index = view.add_l2ndb(l2ndb) + end view.show_l2ndb(l2ndb_index, view.active_cellview_index) end @@ -1525,6 +1565,30 @@ CODE end end + def _generator + @generator + end + + def _generator=(g) + @generator = g + end + + def _rdb_index + @rdb_index + end + + def _rdb_index=(i) + @rdb_index = i + end + + def _l2ndb_index + @l2ndb_index + end + + def _l2ndb_index=(i) + @l2ndb_index = i + end + private def _make_string(v) @@ -1691,7 +1755,7 @@ CODE @layout_sources[name] = src src end - + end end diff --git a/src/drc/drc/built-in-macros/_drc_netter.rb b/src/drc/drc/built-in-macros/_drc_netter.rb index 400acd91b..1a7f70ef6 100644 --- a/src/drc/drc/built-in-macros/_drc_netter.rb +++ b/src/drc/drc/built-in-macros/_drc_netter.rb @@ -407,6 +407,9 @@ module DRC @l2n = RBA::LayoutToNetlist::new(layout.top_cell.name, layout.dbu) end + @l2n.name = "DRC" + @l2n.generator = @engine._generator + end def register_layer(data) diff --git a/src/drc/drc/built-in-macros/drc_interpreters.lym b/src/drc/drc/built-in-macros/drc_interpreters.lym index 3445c815a..6ada00b60 100644 --- a/src/drc/drc/built-in-macros/drc_interpreters.lym +++ b/src/drc/drc/built-in-macros/drc_interpreters.lym @@ -17,37 +17,39 @@ module DRC - def DRC.execute_drc(_macro) + def DRC.execute_drc(macro, generator, rdb_index = nil) - _timer = RBA::Timer::new - _timer.start - _drc = DRCEngine::new + timer = RBA::Timer::new + timer.start + drc = DRCEngine::new + drc._rdb_index = rdb_index + drc._generator = generator begin # Set a debugger scope so that our errors end up with the debugger set to the DRC's line - RBA::MacroExecutionContext::set_debugger_scope(_macro.path) + RBA::MacroExecutionContext::set_debugger_scope(macro.path) # No verbosity set in drc engine - we cannot use the engine's logger - RBA::Logger::verbosity >= 10 && RBA::Logger::info("Running #{_macro.path}") - _drc.instance_eval(_macro.text, _macro.path) + RBA::Logger::verbosity >= 10 && RBA::Logger::info("Running #{macro.path}") + drc.instance_eval(macro.text, macro.path) # Remove the debugger scope RBA::MacroExecutionContext::remove_debugger_scope rescue => ex - _drc.error("In #{_macro.path}: #{ex.to_s}") + drc.error("In #{macro.path}: #{ex.to_s}") RBA::MacroExecutionContext::ignore_next_exception raise ex ensure # cleans up and creates layout and report views - _drc._finish + drc._finish end - _timer.stop - _drc.info("Total run time: #{'%.3f'%(_timer.sys+_timer.user)}s") + timer.stop + drc.info("Total run time: #{'%.3f'%(timer.sys+timer.user)}s") end @@ -55,7 +57,9 @@ module DRC class DRCInterpreter < RBA::MacroInterpreter # Constructor - def initialize + def initialize(recipe) + + @recipe = recipe # Make the DSL use ruby syntax highlighting self.syntax_scheme = "ruby" @@ -74,7 +78,7 @@ module DRC # Implements the execute method def execute(macro) - DRC::execute_drc(macro) + DRC::execute_drc(macro, @recipe.generator("script" => macro.path)) end end @@ -83,7 +87,9 @@ module DRC class DRCPlainTextInterpreter < RBA::MacroInterpreter # Constructor - def initialize + def initialize(recipe) + + @recipe = recipe # Make the DSL use ruby syntax highlighting self.syntax_scheme = "ruby" @@ -99,14 +105,40 @@ module DRC # Implements the execute method def execute(macro) - DRC::execute_drc(macro) + DRC::execute_drc(macro, @recipe.generator("script" => macro.path)) end end + # A recipe implementation allowing the LVS run to be redone + class DRCRecipe < RBA::Recipe + + def initialize + super("drc", "DRC recipe") + end + + def execute(params) + + script = params["script"] + if ! script + return + end + + macro = RBA::Macro::macro_by_path(script) + macro || raise("Can't find DRC script #{script} - unable to re-run") + + DRC::execute_drc(macro, self.generator("script" => script), params["rdb_index"]) + + end + + end + + # Register the recipe + drc_recipe = DRCRecipe::new + # Register the new interpreters - DRCInterpreter::new - DRCPlainTextInterpreter::new + DRCInterpreter::new(drc_recipe) + DRCPlainTextInterpreter::new(drc_recipe) end diff --git a/src/gsi/gsi/gsiDeclTl.cc b/src/gsi/gsi/gsiDeclTl.cc index c282c33c8..9243cbcfb 100644 --- a/src/gsi/gsi/gsiDeclTl.cc +++ b/src/gsi/gsi/gsiDeclTl.cc @@ -27,6 +27,7 @@ #include "tlProgress.h" #include "tlExpression.h" #include "tlGlobPattern.h" +#include "tlRecipe.h" // ---------------------------------------------------------------- // Logger binding @@ -640,4 +641,87 @@ Class decl_GlobPattern ("tl", "GlobPattern", "This class has been introduced in version 0.26." ); +class Recipe_Impl + : public tl::Recipe, public gsi::ObjectBase +{ +public: + Recipe_Impl (const std::string &name, const std::string &description) + : tl::Recipe (name, description) + { + // makes the object owned by the C++ side (registrar). This way we don't need to keep a + // singleton instance. + keep (); + } + + virtual tl::Variant execute (const std::map ¶ms) const + { + if (execute_cb.can_issue ()) { + return execute_cb.issue &> (&tl::Recipe::execute, params); + } else { + return tl::Variant (); + } + } + + gsi::Callback execute_cb; +}; + +} + +namespace tl +{ + template <> struct type_traits : public type_traits { }; +} + +namespace gsi +{ + +static Recipe_Impl *make_recipe (const std::string &name, const std::string &description) +{ + return new Recipe_Impl (name, description); +} + +Class decl_Recipe_Impl ("tl", "Recipe", + gsi::constructor ("new", &make_recipe, gsi::arg ("name"), gsi::arg ("description", std::string (), "\"\""), + "@brief Creates a new recipe object with the given name and (optional) description" + ) + + gsi::method ("name", &Recipe_Impl::name, + "@brief Gets the name of the recipe." + ) + + gsi::method ("description", &Recipe_Impl::description, + "@brief Gets the description of the recipe." + ) + + gsi::method ("make", &Recipe_Impl::make, gsi::arg ("generator"), gsi::arg ("add_params", std::map (), "{}"), + "@brief Executes the recipe given by the generator string.\n" + "The generator string is the one delivered with \\generator.\n" + "Additional parameters can be passed in \"add_params\". They have lower priority than the parameters " + "kept inside the generator string." + ) + + gsi::method ("generator", &Recipe_Impl::generator, gsi::arg ("params"), + "@brief Delivers the generator string from the given parameters.\n" + "The generator string can be used with \\make to re-run the recipe." + ) + + gsi::callback ("execute", &Recipe_Impl::execute, &Recipe_Impl::execute_cb, gsi::arg ("params"), + "@brief Reimplement this method to provide the functionality of the recipe.\n" + "This method is supposed to re-run the recipe with the given parameters and deliver the " + "the intended output object." + ), + "@brief A facility for providing reproducable recipes\n" + "The idea of this facility is to provide a service by which an object\n" + "can be reproduced in a parametrized way. The intended use case is a \n" + "DRC report for example, where the DRC script is the generator.\n" + "\n" + "In this use case, the DRC engine will register a recipe. It will \n" + "put the serialized version of the recipe into the DRC report. If the \n" + "user requests a re-run of the DRC, the recipe will be called and \n" + "the implementation is supposed to deliver a new database.\n" + "\n" + "To register a recipe, reimplement the Recipe class and create an\n" + "instance. To serialize a recipe, use \"generator\", to execute the\n" + "recipe, use \"make\".\n" + "\n" + "Parameters are kept as a generic key/value map.\n" + "\n" + "This class has been introduced in version 0.26." +); + } diff --git a/src/klayout.pro b/src/klayout.pro index 226b13f29..e230d5efb 100644 --- a/src/klayout.pro +++ b/src/klayout.pro @@ -89,12 +89,12 @@ plugins.depends += lib rdb db plugins.depends += lay ant - laybasic.depends += rdb + lym.depends += gsi $$LANG_DEPENDS + laybasic.depends += rdb lym ant.depends += laybasic img.depends += laybasic edt.depends += laybasic - lym.depends += gsi $$LANG_DEPENDS - lay.depends += laybasic ant img edt lym + lay.depends += laybasic ant img edt klayout_main.depends += plugins $$MAIN_DEPENDS } diff --git a/src/lay/lay/doc/about/drc_ref_global.xml b/src/lay/lay/doc/about/drc_ref_global.xml index 0b3b3b2a6..ef89cacdd 100644 --- a/src/lay/lay/doc/about/drc_ref_global.xml +++ b/src/lay/lay/doc/about/drc_ref_global.xml @@ -204,6 +204,30 @@ See Netter#device_scaling Use this class with extract_devices to specify extraction of a planar diode

+

"dmos3" - Supplies the DMOS3 transistor extractor class

+ +

Usage:

+
    +
  • dmos3(name)
    • +
+

+Use this class with extract_devices to specify extraction of a +three-terminal DMOS transistor. A DMOS transistor is essentially +the same than a MOS transistor, but source and drain are +separated. +

+

"dmos4" - Supplies the MOS4 transistor extractor class

+ +

Usage:

+
    +
  • dmos4(name)
    • +
+

+Use this class with extract_devices to specify extraction of a +four-terminal DMOS transistor. A DMOS transistor is essentially +the same than a MOS transistor, but source and drain are +separated. +

"edge" - Creates an edge object

Usage:

diff --git a/src/lay/lay/doc/about/layer_sources.xml b/src/lay/lay/doc/about/layer_sources.xml index a8a8d8ea1..d914b9c3d 100644 --- a/src/lay/lay/doc/about/layer_sources.xml +++ b/src/lay/lay/doc/about/layer_sources.xml @@ -7,7 +7,7 @@

KLayout implements a concept of "layer views". The layer list is made up of such layer views. - A "view" is bascically a specification of what is shown how. + A "view" is basically a specification of what is shown how. The "how" part is given by the colors, stipples, styles etc. The "what" part is given by the source specification.

diff --git a/src/lay/lay/doc/manual/bjt_ex_layout.png b/src/lay/lay/doc/manual/bjt_ex_layout.png index c896b7308..ffbb7e4b4 100644 Binary files a/src/lay/lay/doc/manual/bjt_ex_layout.png and b/src/lay/lay/doc/manual/bjt_ex_layout.png differ diff --git a/src/lay/lay/doc/manual/bjt_ex_tb.png b/src/lay/lay/doc/manual/bjt_ex_tb.png index 2f605fb5a..50f4053fd 100644 Binary files a/src/lay/lay/doc/manual/bjt_ex_tb.png and b/src/lay/lay/doc/manual/bjt_ex_tb.png differ diff --git a/src/lay/lay/doc/manual/bjt_ex_tc.png b/src/lay/lay/doc/manual/bjt_ex_tc.png index 90fbaddc2..e4b1d158f 100644 Binary files a/src/lay/lay/doc/manual/bjt_ex_tc.png and b/src/lay/lay/doc/manual/bjt_ex_tc.png differ diff --git a/src/lay/lay/doc/manual/bjt_ex_te.png b/src/lay/lay/doc/manual/bjt_ex_te.png index 882bf5da4..079a2208b 100644 Binary files a/src/lay/lay/doc/manual/bjt_ex_te.png and b/src/lay/lay/doc/manual/bjt_ex_te.png differ diff --git a/src/lay/lay/doc/manual/bjt_ex_ts.png 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b/src/lay/lay/doc/manual/diode_ex_tc.png differ diff --git a/src/lay/lay/doc/manual/inv.png b/src/lay/lay/doc/manual/inv.png index 64286e60a..67373a981 100644 Binary files a/src/lay/lay/doc/manual/inv.png and b/src/lay/lay/doc/manual/inv.png differ diff --git a/src/lay/lay/doc/manual/inv_no_transistors.png b/src/lay/lay/doc/manual/inv_no_transistors.png index 27705f5c3..51a0de2ea 100644 Binary files a/src/lay/lay/doc/manual/inv_no_transistors.png and b/src/lay/lay/doc/manual/inv_no_transistors.png differ diff --git a/src/lay/lay/doc/manual/inv_transistors.png b/src/lay/lay/doc/manual/inv_transistors.png index 115b39362..c9df73a89 100644 Binary files a/src/lay/lay/doc/manual/inv_transistors.png and b/src/lay/lay/doc/manual/inv_transistors.png differ diff --git a/src/lay/lay/doc/manual/inv_with_diodes.png b/src/lay/lay/doc/manual/inv_with_diodes.png index 1cd892c9c..f8d67e03d 100644 Binary files a/src/lay/lay/doc/manual/inv_with_diodes.png and b/src/lay/lay/doc/manual/inv_with_diodes.png differ diff --git a/src/lay/lay/doc/manual/lvs_compare.xml b/src/lay/lay/doc/manual/lvs_compare.xml index 221bee1f6..72e60825e 100644 --- a/src/lay/lay/doc/manual/lvs_compare.xml +++ b/src/lay/lay/doc/manual/lvs_compare.xml @@ -119,11 +119,59 @@ same_device_classes("NMOS_IN_LAYOUT", "NMOS_IN_SCHEMATIC")

To eliminate all capacitors with a capacitance value below a certain threshold, use the - max_caps function. This will + min_caps function. This will eliminate all capacitances with a value <= 0.1fF:

- 
max_caps(1e-16)
+ 
min_caps(1e-16)
+ +

Compare and netlist hierarchy

+ +

+ Good layouts are built hierarchically and the netlist compare can make use + of hierarchy. "Hierarchically" means that a circuit is built from cells + which itself map to subcircuits of the schematic netlist. The netlist + extractor tries hard to maintain the hierarchy and the netlist compare + will utilize the hierarchy to provide more meaningful reports and enable + a bottom-up design approach. +

+ +

+ Given a hierarchical layout and schematic netlist, the compare algorithm + will work bottom-up: it will first compare the leaf circuits (circuits without + subcircuit calls) and if those match, it will continue with the calling + circuits. This approach is more efficient and fosters a clean relationship + between layout and schematic netlist. +

+ +

+ To enable hierarchical extraction, you must use "deep" mode (deep). + If the deep mode statement is missing, the layout netlist will be flat (i.e. without + subcircuits). +

+ +

+ The second useful feature is "align" (align). + This statement will remove circuits from the layout or schematic netlist which are + unknown in the other netlist. Often, layouts contain helper cells which are not + corresponding to a circuit (e.g. via cells). These are removed in this step. Eventually, + this step will also flatten the schematic netlist if the layout has been extracted + in a flat way. +

+ +

+ In general, it's a good idea to include "align" before the "compare" step. +

+ +

+ A very useful side effect of "align" is this: it will remove circuits above the + top level circuit of either side. So it will eventually render a sub-tree from + the circuit tree and use that for compare. This enables subcell verification: + by selecting a subcell in the layout hierarchy, an "align"-enabled LVS script will + compare this cell against the corresponding subcircuit in the schematic netlist. + It will ignore the parent hierarchy of this subcircuit. This way, you can work yourself + upwards in the hierarchy and fix LVS errors cell by cell with the same schematic netlist. +

How the compare algorithm works

diff --git a/src/lay/lay/doc/manual/lvs_device_extractors.xml b/src/lay/lay/doc/manual/lvs_device_extractors.xml index c3d07fd71..4af511c2a 100644 --- a/src/lay/lay/doc/manual/lvs_device_extractors.xml +++ b/src/lay/lay/doc/manual/lvs_device_extractors.xml @@ -187,6 +187,27 @@ extract_devices(mos4(model_name), { "SD" => (active - poly) & pplus, "G" =>

+

Diffusion MOS transistor extractor (dmos3 and dmos4)

+ +

+ DMOS devices are basically identical to MOS devices, but for those source and drain are + separated. This is often the case for diffusion MOS transistory, hence this name. +

+ +

+ DMOS and MOS devices share the same device class. DMOS devices are configured + such that source and drain cannot be swapped. The netlist compare will report + source/drain swapping as errors for such devices. +

+ +

+ DMOS transistors are recognized by their gate ("G" input), source ("S" input) and drain ("D" input) + regions. Source and drain needs to be separated from the gate shape. The touching edges of gate and + source/drain regions define the width of the device, the perpendicular dimension the gate length. + The terminal output layers for DMOS devices are the same than for MOS devices: "tS" for source, + "tD" for drain, "tG" for gate, "tB" for bulk (4-terminal version). +

+

Bipolar transistor extractor (bjt3 and bjt4)

diff --git a/src/lay/lay/doc/manual/lvs_io.xml b/src/lay/lay/doc/manual/lvs_io.xml index 37ab399e0..3e66a3624 100644 --- a/src/lay/lay/doc/manual/lvs_io.xml +++ b/src/lay/lay/doc/manual/lvs_io.xml @@ -189,12 +189,14 @@ X$2 VSS IN OUT SUBSTRATE NMOS PARAMS: L=0.25 W=0.9 AS=0.405 AD=0.405 PS=2.7 class SubcircuitModelsReader < RBA::NetlistSpiceReaderDelegate + # implements the delegate interface: # says we want to catch these subcircuits as devices def wants_subcircuit(name) name == "NMOS" || name == "PMOS" end - # translate the element + # implements the delegate interface: + # take and translate the element def element(circuit, el, name, model, value, nets, params) if el != "X" @@ -221,9 +223,13 @@ class SubcircuitModelsReader < RBA::NetlistSpiceReaderDelegate [ "S", "G", "D", "B" ].each_with_index do |t,index| device.connect_terminal(t, nets[index]) end - params.each do |p,value| - device.set_parameter(p, value) - end + + # parameters in the model are given in micrometer units, so + # we need to translate the parameter values from SI to um values: + device.set_parameter("W", (params["W"] || 0.0) * 1e6) + device.set_parameter("L", (params["L"] || 0.0) * 1e6) + + return true end diff --git a/src/lay/lay/doc/manual/mos_ex_layout.png b/src/lay/lay/doc/manual/mos_ex_layout.png index 9e84462d9..e55f5d9f2 100644 Binary files a/src/lay/lay/doc/manual/mos_ex_layout.png and b/src/lay/lay/doc/manual/mos_ex_layout.png differ diff --git a/src/lay/lay/doc/manual/mos_ex_tb.png b/src/lay/lay/doc/manual/mos_ex_tb.png index 0c0979484..d4cee108e 100644 Binary files a/src/lay/lay/doc/manual/mos_ex_tb.png and b/src/lay/lay/doc/manual/mos_ex_tb.png differ diff --git a/src/lay/lay/doc/manual/mos_ex_td.png b/src/lay/lay/doc/manual/mos_ex_td.png index d723abc34..b9f996858 100644 Binary files a/src/lay/lay/doc/manual/mos_ex_td.png and b/src/lay/lay/doc/manual/mos_ex_td.png differ diff --git a/src/lay/lay/doc/manual/mos_ex_tg.png b/src/lay/lay/doc/manual/mos_ex_tg.png index a488d7350..d4cc2c9a1 100644 Binary files a/src/lay/lay/doc/manual/mos_ex_tg.png and b/src/lay/lay/doc/manual/mos_ex_tg.png differ diff --git a/src/lay/lay/doc/manual/mos_ex_ts.png b/src/lay/lay/doc/manual/mos_ex_ts.png index 9f459cfeb..97b499252 100644 Binary files a/src/lay/lay/doc/manual/mos_ex_ts.png and b/src/lay/lay/doc/manual/mos_ex_ts.png differ diff --git a/src/lay/lay/doc/manual/res_ex_layout.png b/src/lay/lay/doc/manual/res_ex_layout.png index 4b16e19ff..ee30d5e9e 100644 Binary files a/src/lay/lay/doc/manual/res_ex_layout.png and b/src/lay/lay/doc/manual/res_ex_layout.png differ diff --git a/src/lay/lay/doc/manual/res_ex_ta.png b/src/lay/lay/doc/manual/res_ex_ta.png index 971633c59..c51954e58 100644 Binary files a/src/lay/lay/doc/manual/res_ex_ta.png and b/src/lay/lay/doc/manual/res_ex_ta.png differ diff --git a/src/lay/lay/doc/manual/res_ex_tb.png b/src/lay/lay/doc/manual/res_ex_tb.png index e25fdce18..b0da153ae 100644 Binary files a/src/lay/lay/doc/manual/res_ex_tb.png and b/src/lay/lay/doc/manual/res_ex_tb.png differ diff --git a/src/lay/lay/doc/manual/res_ex_tw.png b/src/lay/lay/doc/manual/res_ex_tw.png index 706b39b5b..a02456c39 100644 Binary files a/src/lay/lay/doc/manual/res_ex_tw.png and b/src/lay/lay/doc/manual/res_ex_tw.png differ diff --git a/src/laybasic/laybasic/MarkerBrowserDialog.ui b/src/laybasic/laybasic/MarkerBrowserDialog.ui index d7c11abb5..1a7dc53d0 100644 --- a/src/laybasic/laybasic/MarkerBrowserDialog.ui +++ b/src/laybasic/laybasic/MarkerBrowserDialog.ui @@ -1,7 +1,8 @@ - + + MarkerBrowserDialog - - + + 0 0 @@ -9,40 +10,75 @@ 553 - + Marker Database Browser - - - 9 - - + + 6 + + 9 + + + 9 + + + 9 + + + 9 + - - + + QFrame::NoFrame - + QFrame::Raised - - + + 0 - + + 0 + + + 0 + + + 0 + + 6 - + + + + File ... + + + QToolButton::InstantPopup + + + + + + + ... on layout + + + + - + Qt::Horizontal - + QSizePolicy::Fixed - + 20 20 @@ -50,152 +86,133 @@ - - - - - 7 - 0 + + + + 1 0 - + QComboBox::AdjustToContentsOnFirstShow - - - + + + Database - - - - ... on layout - - - - - - - - 7 - 0 + + + + 1 0 - + QComboBox::AdjustToContentsOnFirstShow - - - - File ... - - - QToolButton::InstantPopup - - - - - - - Qt::Vertical - - - QSizePolicy::Fixed - - - - 20 - 10 - - - - - - - Qt::Horizontal - - - - - - + + QFrame::NoFrame - + QFrame::Raised - - - 0 - - + + 6 + + 0 + + + 0 + + + 0 + + + 0 + - - + + 1 - - - - 0 - - + + + 6 + + 0 + + + 0 + + + 0 + + + 0 + - - - - 13 - 13 + + + 0 0 - + QFrame::NoFrame - + QFrame::Raised - - - - 0 - - + + + 6 + + 0 + + + 0 + + + 0 + + + 0 + - - - Choose "Open" from the "File ..." menu + + + Choose "Open" from the "File ..." menu to load a marker database - + Qt::AlignCenter - + true @@ -208,40 +225,49 @@ to load a marker database - - + + Qt::Horizontal - - + + QFrame::NoFrame - + QFrame::Raised - - - 0 - - + + 6 + + 0 + + + 0 + + + 0 + + + 0 + - - + + Configure - + Qt::Horizontal - + 40 20 @@ -250,8 +276,8 @@ to load a marker database - - + + Close @@ -266,6 +292,7 @@ to load a marker database rdb::MarkerBrowserPage QFrame

rdbMarkerBrowserPage.h
+ 1 @@ -282,11 +309,11 @@ to load a marker database MarkerBrowserDialog accept() - + 837 441 - + 881 387 diff --git a/src/laybasic/laybasic/MarkerBrowserPage.ui b/src/laybasic/laybasic/MarkerBrowserPage.ui index 682d9ae9c..d352c1916 100644 --- a/src/laybasic/laybasic/MarkerBrowserPage.ui +++ b/src/laybasic/laybasic/MarkerBrowserPage.ui @@ -13,7 +13,7 @@ Form - + 6 @@ -29,6 +29,73 @@ 0 + + + + + 0 + 0 + + + + QFrame::NoFrame + + + QFrame::Raised + + + + 0 + + + 0 + + + 0 + + + 0 + + + + + ... + + + + :/run.png:/run.png + + + F5 + + + true + + + + + + + Qt::Vertical + + + + 20 + 11 + + + + + + + + Qt::Horizontal + + + + + + @@ -63,69 +130,6 @@ 6 - - - - ... - - - - :/down.png:/down.png - - - - - - - ... - - - - :/up.png:/up.png - - - - - - - - 0 - 0 - - - - - 0 - 4 - - - - Qt::ActionsContextMenu - - - QAbstractItemView::ExtendedSelection - - - QAbstractItemView::SelectRows - - - true - - - true - - - true - - - - - - - Directory - - - @@ -237,6 +241,69 @@ + + + + ... + + + + :/down.png:/down.png + + + + + + + ... + + + + :/up.png:/up.png + + + + + + + + 0 + 0 + + + + + 0 + 4 + + + + Qt::ActionsContextMenu + + + QAbstractItemView::ExtendedSelection + + + QAbstractItemView::SelectRows + + + true + + + true + + + true + + + + + + + Directory + + + diff --git a/src/laybasic/laybasic/NetlistBrowserPage.ui b/src/laybasic/laybasic/NetlistBrowserPage.ui index 84373f842..19d7438c1 100644 --- a/src/laybasic/laybasic/NetlistBrowserPage.ui +++ b/src/laybasic/laybasic/NetlistBrowserPage.ui @@ -132,6 +132,23 @@ + + + + ... + + + + :/run.png:/run.png + + + F5 + + + true + + + diff --git a/src/laybasic/laybasic/gsiDeclLayLayoutView.cc b/src/laybasic/laybasic/gsiDeclLayLayoutView.cc index 129ca2851..2e0b3d44c 100644 --- a/src/laybasic/laybasic/gsiDeclLayLayoutView.cc +++ b/src/laybasic/laybasic/gsiDeclLayLayoutView.cc @@ -218,11 +218,17 @@ static db::LayoutVsSchematic *get_lvsdb (lay::LayoutView *view, unsigned int ind return dynamic_cast (db); } -static void add_lvsdb (lay::LayoutView *view, db::LayoutVsSchematic *lvsdb) +static unsigned int add_lvsdb (lay::LayoutView *view, db::LayoutVsSchematic *lvsdb) { - view->add_l2ndb (lvsdb); + return view->add_l2ndb (lvsdb); } +static unsigned int replace_lvsdb (lay::LayoutView *view, unsigned int db_index, db::LayoutVsSchematic *lvsdb) +{ + return view->replace_l2ndb (db_index, lvsdb); +} + + // this binding returns a const pointer which is not converted into a copy by RBA static lay::LayerPropertiesNodeRef insert_layer1 (lay::LayoutView *view, const lay::LayerPropertiesConstIterator &iter, const lay::LayerProperties &props) { @@ -1442,7 +1448,7 @@ Class decl_LayoutView (QT_EXTERNAL_BASE (QWidget) "lay", "Layou "@return The \\ReportDatabase object or nil if the index is not valid" ) + gsi::method ("add_rdb", &lay::LayoutView::add_rdb, gsi::arg ("db"), - "@brief Adds the given database to the view\n" + "@brief Adds the given report database to the view\n" "\n" "This method will add an existing database to the view. It will then appear in the marker database browser.\n" "A similar method is \\create_rdb which will create a new database within the view.\n" @@ -1451,6 +1457,15 @@ Class decl_LayoutView (QT_EXTERNAL_BASE (QWidget) "lay", "Layou "\n" "This method has been added in version 0.26." ) + + gsi::method ("replace_rdb", &lay::LayoutView::replace_rdb, gsi::arg ("db_index"), gsi::arg ("db"), + "@brief Replaces the report database with the given index\n" + "\n" + "If the index is not valid, the database will be added to the view (see \\add_rdb).\n" + "\n" + "@return The index of the database within the view (see \\rdb)\n" + "\n" + "This method has been added in version 0.26." + ) + gsi::method_ext ("create_rdb", &create_rdb, gsi::arg ("name"), "@brief Creates a new report database and returns the index of the new database\n" "@param name The name of the new report database\n" @@ -1490,7 +1505,7 @@ Class decl_LayoutView (QT_EXTERNAL_BASE (QWidget) "lay", "Layou "This method has been added in version 0.26." ) + gsi::method ("add_l2ndb", &lay::LayoutView::add_l2ndb, gsi::arg ("db"), - "@brief Adds the given database to the view\n" + "@brief Adds the given netlist database to the view\n" "\n" "This method will add an existing database to the view. It will then appear in the netlist database browser.\n" "A similar method is \\create_l2ndb which will create a new database within the view.\n" @@ -1499,6 +1514,15 @@ Class decl_LayoutView (QT_EXTERNAL_BASE (QWidget) "lay", "Layou "\n" "This method has been added in version 0.26." ) + + gsi::method ("replace_l2ndb", &lay::LayoutView::replace_l2ndb, gsi::arg ("db_index"), gsi::arg ("db"), + "@brief Replaces the netlist database with the given index\n" + "\n" + "If the index is not valid, the database will be added to the view (see \\add_lvsdb).\n" + "\n" + "@return The index of the database within the view (see \\lvsdb)\n" + "\n" + "This method has been added in version 0.26." + ) + gsi::method_ext ("create_l2ndb", &create_l2ndb, gsi::arg ("name"), "@brief Creates a new netlist database and returns the index of the new database\n" "@param name The name of the new netlist database\n" @@ -1532,6 +1556,15 @@ Class decl_LayoutView (QT_EXTERNAL_BASE (QWidget) "lay", "Layou "\n" "This method has been added in version 0.26." ) + + gsi::method_ext ("replace_lvsdb", &replace_lvsdb, gsi::arg ("db_index"), gsi::arg ("db"), + "@brief Replaces the database with the given index\n" + "\n" + "If the index is not valid, the database will be added to the view (see \\add_lvsdb).\n" + "\n" + "@return The index of the database within the view (see \\lvsdb)\n" + "\n" + "This method has been added in version 0.26." + ) + gsi::method_ext ("create_lvsdb", &create_lvsdb, gsi::arg ("name"), "@brief Creates a new netlist database and returns the index of the new database\n" "@param name The name of the new netlist database\n" diff --git a/src/laybasic/laybasic/layLayoutView.cc b/src/laybasic/laybasic/layLayoutView.cc index 3249333e9..531a604ca 100644 --- a/src/laybasic/laybasic/layLayoutView.cc +++ b/src/laybasic/laybasic/layLayoutView.cc @@ -7213,6 +7213,32 @@ LayoutView::add_l2ndb (db::LayoutToNetlist *l2ndb) return (unsigned int)(m_l2ndbs.size () - 1); } +unsigned int +LayoutView::replace_l2ndb (unsigned int db_index, db::LayoutToNetlist *l2ndb) +{ + tl_assert (l2ndb != 0); + + if (db_index < m_l2ndbs.size ()) { + + // keep the name as it is used for reference in the browser for example + std::string n = m_l2ndbs [db_index]->name (); + l2ndb->set_name (n); + + delete m_l2ndbs [db_index]; + m_l2ndbs [db_index] = l2ndb; + + // Mark this object as owned by us (for GSI) + l2ndb->keep (); + + l2ndb_list_changed_event (); + + return db_index; + + } else { + return add_l2ndb (l2ndb); + } +} + db::LayoutToNetlist * LayoutView::get_l2ndb (int index) { @@ -7255,7 +7281,7 @@ LayoutView::remove_l2ndb (unsigned int index) unsigned int LayoutView::add_rdb (rdb::Database *rdb) { - make_unique_name (rdb, m_l2ndbs.begin (), m_l2ndbs.end ()); + make_unique_name (rdb, m_rdbs.begin (), m_rdbs.end ()); m_rdbs.push_back (rdb); // Mark this object as owned by us (for GSI) @@ -7266,6 +7292,32 @@ LayoutView::add_rdb (rdb::Database *rdb) return (unsigned int)(m_rdbs.size () - 1); } +unsigned int +LayoutView::replace_rdb (unsigned int db_index, rdb::Database *rdb) +{ + tl_assert (rdb != 0); + + if (db_index < m_rdbs.size ()) { + + // keep name because it's used for reference in the browser for example + std::string n = m_rdbs [db_index]->name (); + rdb->set_name (n); + + delete m_rdbs [db_index]; + m_rdbs [db_index] = rdb; + + // Mark this object as owned by us (for GSI) + rdb->keep (); + + rdb_list_changed_event (); + + return db_index; + + } else { + return add_rdb (rdb); + } +} + rdb::Database * LayoutView::get_rdb (int index) { diff --git a/src/laybasic/laybasic/layLayoutView.h b/src/laybasic/laybasic/layLayoutView.h index cf5cbc8b9..d562d74ca 100644 --- a/src/laybasic/laybasic/layLayoutView.h +++ b/src/laybasic/laybasic/layLayoutView.h @@ -2285,6 +2285,17 @@ public: */ unsigned int add_rdb (rdb::Database *rdb); + /** + * @brief Replaces a marker database + * + * The layout view will become owner of the database. + * If the index is not valid, the database will be added and the new index will be returned. + * + * @param db_index The index of the database to replace + * @param rdb The database to add + */ + unsigned int replace_rdb (unsigned int db_index, rdb::Database *rdb); + /** * @brief Get the marker database by index * @@ -2340,6 +2351,17 @@ public: */ unsigned int add_l2ndb (db::LayoutToNetlist *l2ndb); + /** + * @brief Replaces a Netlist database + * + * The layout view will become owner of the database. + * If the index is not valid, the database will be added and the new index will be returned. + * + * @param db_index The index of the database to replace + * @param l2ndb The database to add + */ + unsigned int replace_l2ndb (unsigned int db_index, db::LayoutToNetlist *l2ndb); + /** * @brief Get the netlist database by index * diff --git a/src/laybasic/laybasic/layNetlistBrowserModel.cc b/src/laybasic/laybasic/layNetlistBrowserModel.cc index 6c7741aef..b1bd0e5e3 100644 --- a/src/laybasic/laybasic/layNetlistBrowserModel.cc +++ b/src/laybasic/laybasic/layNetlistBrowserModel.cc @@ -824,6 +824,9 @@ static std::string device_parameter_string (const db::Device *device) { std::string s; + if (! device || ! device->device_class ()) { + return s; + } bool first = true; const std::vector &pd = device->device_class ()->parameter_definitions (); diff --git a/src/laybasic/laybasic/layNetlistBrowserPage.cc b/src/laybasic/laybasic/layNetlistBrowserPage.cc index ee0474460..b47b7fd09 100644 --- a/src/laybasic/laybasic/layNetlistBrowserPage.cc +++ b/src/laybasic/laybasic/layNetlistBrowserPage.cc @@ -32,6 +32,7 @@ #include "layNetExportDialog.h" #include "tlProgress.h" #include "tlExceptions.h" +#include "tlRecipe.h" #include "dbLayoutToNetlist.h" #include "dbNetlistDeviceClasses.h" #include "dbCellMapping.h" @@ -124,6 +125,7 @@ NetlistBrowserPage::NetlistBrowserPage (QWidget * /*parent*/) m_update_needed (true), mp_info_dialog (0), dm_update_highlights (this, &NetlistBrowserPage::update_highlights), + dm_rerun_macro (this, &NetlistBrowserPage::rerun_macro), m_cell_context_cache (0) { Ui::NetlistBrowserPage::setupUi (this); @@ -188,6 +190,7 @@ NetlistBrowserPage::NetlistBrowserPage (QWidget * /*parent*/) connect (m_show_all_action, SIGNAL (triggered ()), this, SLOT (show_all_clicked ())); connect (info_button, SIGNAL (pressed ()), this, SLOT (info_button_pressed ())); + connect (rerun_button, SIGNAL (pressed ()), this, SLOT (rerun_button_pressed ())); connect (find_button, SIGNAL (pressed ()), this, SLOT (find_button_pressed ())); connect (forward, SIGNAL (clicked ()), this, SLOT (navigate_forward ())); connect (backward, SIGNAL (clicked ()), this, SLOT (navigate_back ())); @@ -585,6 +588,32 @@ NetlistBrowserPage::navigate_forward () } } +void +NetlistBrowserPage::rerun_button_pressed () +{ + // NOTE: we use deferred execution, because otherwise the button won't get repainted properly + dm_rerun_macro (); +} + +void +NetlistBrowserPage::rerun_macro () +{ + if (! mp_database->generator ().empty ()) { + + std::map add_pars; + + for (unsigned int i = 0; i < mp_view->num_l2ndbs (); ++i) { + if (mp_view->get_l2ndb (i) == mp_database.get ()) { + add_pars["l2ndb_index"] = tl::Variant (int (i)); + break; + } + } + + tl::Recipe::make (mp_database->generator (), add_pars); + + } +} + void NetlistBrowserPage::info_button_pressed () { @@ -741,6 +770,17 @@ NetlistBrowserPage::set_db (db::LayoutToNetlist *l2ndb) db::LayoutVsSchematic *lvsdb = dynamic_cast (l2ndb); mp_database.reset (l2ndb); + rerun_button->setEnabled (mp_database.get () && ! mp_database->generator ().empty ()); + if (rerun_button->isEnabled ()) { + QString shortcut; + if (! rerun_button->shortcut ().isEmpty ()) { + shortcut = QString::fromUtf8 (" (%1)").arg (rerun_button->shortcut ().toString ()); + } + rerun_button->setToolTip (tl::to_qstring (tl::to_string (tr ("Run ")) + mp_database->generator ()) + shortcut); + } else { + rerun_button->setToolTip (QString ()); + } + show_netlist->setVisible (lvsdb != 0); show_xref->setVisible (lvsdb != 0); diff --git a/src/laybasic/laybasic/layNetlistBrowserPage.h b/src/laybasic/laybasic/layNetlistBrowserPage.h index 2bde27cec..1440a13b0 100644 --- a/src/laybasic/laybasic/layNetlistBrowserPage.h +++ b/src/laybasic/laybasic/layNetlistBrowserPage.h @@ -169,6 +169,7 @@ public slots: private slots: void show_all_clicked (); void info_button_pressed (); + void rerun_button_pressed (); void find_button_pressed (); void anchor_clicked (const QString &url); void navigate_back (); @@ -212,6 +213,7 @@ private: std::vector m_current_circuits; lay::NetInfoDialog *mp_info_dialog; tl::DeferredMethod dm_update_highlights; + tl::DeferredMethod dm_rerun_macro; db::ContextCache m_cell_context_cache; void set_db (db::LayoutToNetlist *l2ndb); @@ -233,6 +235,7 @@ private: bool produce_highlights_for_subcircuit (const db::SubCircuit *subcircuit, size_t &n_markers, const std::vector &tv); bool produce_highlights_for_circuit (const db::Circuit *circuit, size_t &n_markers, const std::vector &tv); void configure_marker (lay::Marker *marker, bool with_fill); + void rerun_macro (); void export_nets (const std::vector *nets); }; diff --git a/src/laybasic/laybasic/laybasic.pro b/src/laybasic/laybasic/laybasic.pro index 5d59bd3af..443343ce1 100644 --- a/src/laybasic/laybasic/laybasic.pro +++ b/src/laybasic/laybasic/laybasic.pro @@ -275,9 +275,9 @@ HEADERS = \ layNetlistBrowserTreeModel.h \ layLibrariesView.h -INCLUDEPATH += $$TL_INC $$GSI_INC $$DB_INC $$RDB_INC -DEPENDPATH += $$TL_INC $$GSI_INC $$DB_INC $$RDB_INC -LIBS += -L$$DESTDIR -lklayout_tl -lklayout_gsi -lklayout_db -lklayout_rdb +INCLUDEPATH += $$TL_INC $$GSI_INC $$DB_INC $$RDB_INC $$LYM_INC +DEPENDPATH += $$TL_INC $$GSI_INC $$DB_INC $$RDB_INC $$LYM_INC +LIBS += -L$$DESTDIR -lklayout_tl -lklayout_gsi -lklayout_db -lklayout_rdb -lklayout_lym INCLUDEPATH += $$QTBASIC_INC DEPENDPATH += $$QTBASIC_INC diff --git a/src/laybasic/laybasic/rdbMarkerBrowserDialog.cc b/src/laybasic/laybasic/rdbMarkerBrowserDialog.cc index 680540389..b599eeb58 100644 --- a/src/laybasic/laybasic/rdbMarkerBrowserDialog.cc +++ b/src/laybasic/laybasic/rdbMarkerBrowserDialog.cc @@ -671,6 +671,7 @@ MarkerBrowserDialog::update_content () m_reload_action->setEnabled (rdb != 0); browser_frame->enable_updates (false); // Avoid building the internal lists several times ... + browser_frame->set_rdb (0); // force update browser_frame->set_rdb (rdb); browser_frame->set_max_marker_count (m_max_marker_count); browser_frame->set_marker_style (m_marker_color, m_marker_line_width, m_marker_vertex_size, m_marker_halo, m_marker_dither_pattern); diff --git a/src/laybasic/laybasic/rdbMarkerBrowserPage.cc b/src/laybasic/laybasic/rdbMarkerBrowserPage.cc index 1948b6f95..ef268bb1b 100644 --- a/src/laybasic/laybasic/rdbMarkerBrowserPage.cc +++ b/src/laybasic/laybasic/rdbMarkerBrowserPage.cc @@ -26,6 +26,7 @@ #include "dbLayoutUtils.h" +#include "tlRecipe.h" #include "layLayoutView.h" #include "layMarker.h" @@ -1463,7 +1464,8 @@ MarkerBrowserPage::MarkerBrowserPage (QWidget * /*parent*/) m_marker_list_sort_order (Qt::DescendingOrder), m_directory_tree_sorted_section (-1), m_directory_tree_sort_order (Qt::DescendingOrder), - mp_plugin_root (0) + mp_plugin_root (0), + dm_rerun_macro (this, &MarkerBrowserPage::rerun_macro) { Ui::MarkerBrowserPage::setupUi (this); @@ -1514,6 +1516,7 @@ MarkerBrowserPage::MarkerBrowserPage (QWidget * /*parent*/) connect (info_text, SIGNAL (anchorClicked (const QUrl &)), this, SLOT (info_anchor_clicked (const QUrl &))); connect (cat_filter, SIGNAL (textEdited (const QString &)), this, SLOT (filter_changed ())); connect (cell_filter, SIGNAL (textEdited (const QString &)), this, SLOT (filter_changed ())); + connect (rerun_button, SIGNAL (pressed ()), this, SLOT (rerun_button_pressed ())); m_show_all_action = new QAction (QObject::tr ("Show All"), this); m_show_all_action->setCheckable (true); @@ -1678,6 +1681,17 @@ MarkerBrowserPage::set_rdb (rdb::Database *database) mp_database = database; + rerun_button->setEnabled (mp_database && ! mp_database->generator ().empty ()); + if (rerun_button->isEnabled ()) { + QString shortcut; + if (! rerun_button->shortcut ().isEmpty ()) { + shortcut = QString::fromUtf8 (" (%1)").arg (rerun_button->shortcut ().toString ()); + } + rerun_button->setToolTip (tl::to_qstring (tl::to_string (tr ("Run ")) + mp_database->generator ()) + shortcut); + } else { + rerun_button->setToolTip (QString ()); + } + QAbstractItemModel *tree_model = directory_tree->model (); MarkerBrowserTreeViewModel *new_model = new MarkerBrowserTreeViewModel (); @@ -2643,6 +2657,32 @@ MarkerBrowserPage::flag_button_clicked () list_model->mark_data_changed (); } +void +MarkerBrowserPage::rerun_button_pressed () +{ + // NOTE: we use deferred execution, because otherwise the button won't get repainted properly + dm_rerun_macro (); +} + +void +MarkerBrowserPage::rerun_macro () +{ + if (! mp_database->generator ().empty ()) { + + std::map add_pars; + + for (unsigned int i = 0; i < mp_view->num_rdbs (); ++i) { + if (mp_view->get_rdb (i) == mp_database) { + add_pars["rdb_index"] = tl::Variant (int (i)); + break; + } + } + + tl::Recipe::make (mp_database->generator (), add_pars); + + } +} + void MarkerBrowserPage::flag_menu_selected () { diff --git a/src/laybasic/laybasic/rdbMarkerBrowserPage.h b/src/laybasic/laybasic/rdbMarkerBrowserPage.h index 66cd279a9..508bbf050 100644 --- a/src/laybasic/laybasic/rdbMarkerBrowserPage.h +++ b/src/laybasic/laybasic/rdbMarkerBrowserPage.h @@ -26,6 +26,7 @@ #include "ui_MarkerBrowserPage.h" #include "rdbMarkerBrowser.h" +#include "tlDeferredExecution.h" #include "dbBox.h" #include @@ -155,6 +156,7 @@ public slots: void dir_down_clicked (); void list_up_clicked (); void list_down_clicked (); + void rerun_button_pressed (); void flag_button_clicked (); void flag_menu_selected (); void important_button_clicked (); @@ -205,6 +207,7 @@ private: int m_directory_tree_sorted_section; Qt::SortOrder m_directory_tree_sort_order; lay::PluginRoot *mp_plugin_root; + tl::DeferredMethod dm_rerun_macro; void release_markers (); void update_marker_list (int selection_mode); @@ -214,6 +217,7 @@ private: void mark_visited (bool visited); void do_update_markers (); void update_info_text (); + void rerun_macro (); }; } // namespace rdb diff --git a/src/lvs/lvs/built-in-macros/_lvs_netter.rb b/src/lvs/lvs/built-in-macros/_lvs_netter.rb index 4b445e3da..26f45bb00 100644 --- a/src/lvs/lvs/built-in-macros/_lvs_netter.rb +++ b/src/lvs/lvs/built-in-macros/_lvs_netter.rb @@ -61,6 +61,9 @@ module LVS @lvs = RBA::LayoutVsSchematic::new(cell.name, layout.dbu) end + @lvs.name = "LVS" + @lvs.generator = @engine._generator + @l2n = @lvs @comparer = RBA::NetlistComparer::new @@ -117,8 +120,16 @@ module LVS nl = _ensure_two_netlists + unmatched_a = @comparer.unmatched_circuits_a(*nl) + + # check whether we're about to flatten away the internal top cell - that's bad + top_cell = l2n_data.internal_top_cell.name + if unmatched_a.find { |c| c.name == top_cell } + raise("Can't find a schematic counterpart for the top cell #{top_cell} - use 'same_circuit' to establish a correspondence") + end + # flatten layout cells for which there is no corresponding schematic circuit - @comparer.unmatched_circuits_a(*nl).each do |c| + unmatched_a.each do |c| @engine.info("Flatten layout cell (no schematic): #{c.name}") nl[0].flatten_circuit(c) end @@ -285,9 +296,13 @@ module LVS ( nl_a, nl_b ) = _ensure_two_netlists dc_a = a && (nl_a.device_class_by_name(a) || raise("Not a valid device class in extracted netlist: #{a}")) - dc_b = b && (nl_b.device_class_by_name(b) || raise("Not a valid device class in reference netlist: #{b}")) + dc_b = b && nl_b.device_class_by_name(b) - @comparer.same_device_classes(dc_a, dc_b) + # NOTE: a device class is allowed to be missing in the reference netlist because the + # device may simply not be used there. + if dc_b + @comparer.same_device_classes(dc_a, dc_b) + end end diff --git a/src/lvs/lvs/built-in-macros/lvs_interpreters.lym b/src/lvs/lvs/built-in-macros/lvs_interpreters.lym index 24a1d0d84..5c6e36eca 100644 --- a/src/lvs/lvs/built-in-macros/lvs_interpreters.lym +++ b/src/lvs/lvs/built-in-macros/lvs_interpreters.lym @@ -17,37 +17,39 @@ module LVS - def LVS.execute_lvs(_macro) + def self.execute_lvs(macro, generator, l2ndb_index = nil) - _timer = RBA::Timer::new - _timer.start - _lvs = LVSEngine::new + timer = RBA::Timer::new + timer.start + lvs = LVSEngine::new + lvs._l2ndb_index = l2ndb_index + lvs._generator = generator begin # Set a debugger scope so that our errors end up with the debugger set to the LVS's line - RBA::MacroExecutionContext::set_debugger_scope(_macro.path) + RBA::MacroExecutionContext::set_debugger_scope(macro.path) # No verbosity set in lvs engine - we cannot use the engine's logger - RBA::Logger::verbosity >= 10 && RBA::Logger::info("Running #{_macro.path}") - _lvs.instance_eval(_macro.text, _macro.path) + RBA::Logger::verbosity >= 10 && RBA::Logger::info("Running #{macro.path}") + lvs.instance_eval(macro.text, macro.path) # Remove the debugger scope RBA::MacroExecutionContext::remove_debugger_scope rescue => ex - _lvs.error("In #{_macro.path}: #{ex.to_s}") + lvs.error("In #{macro.path}: #{ex.to_s}") RBA::MacroExecutionContext::ignore_next_exception raise ex ensure # cleans up and creates layout and report views - _lvs._finish + lvs._finish end - _timer.stop - _lvs.info("Total run time: #{'%.3f'%(_timer.sys+_timer.user)}s") + timer.stop + lvs.info("Total run time: #{'%.3f'%(timer.sys+timer.user)}s") end @@ -55,7 +57,9 @@ module LVS class LVSInterpreter < RBA::MacroInterpreter # Constructor - def initialize + def initialize(recipe) + + @recipe = recipe # Make the DSL use ruby syntax highlighting self.syntax_scheme = "ruby" @@ -80,7 +84,7 @@ module LVS # Implements the execute method def execute(macro) - LVS::execute_lvs(macro) + LVS::execute_lvs(macro, @recipe.generator("script" => macro.path)) end end @@ -89,7 +93,9 @@ module LVS class LVSPlainTextInterpreter < RBA::MacroInterpreter # Constructor - def initialize + def initialize(recipe) + + @recipe = recipe # Make the DSL use ruby syntax highlighting self.syntax_scheme = "ruby" @@ -105,15 +111,41 @@ module LVS # Implements the execute method def execute(macro) - LVS::execute_lvs(macro) + LVS::execute_lvs(macro, @recipe.generator("script" => macro.path)) end end + + # A recipe implementation allowing the LVS run to be redone + class LVSRecipe < RBA::Recipe + + def initialize + super("lvs", "LVS recipe") + end + + def execute(params) + + script = params["script"] + if ! script + return + end + + macro = RBA::Macro::macro_by_path(script) + macro || raise("Can't find LVS script #{script} - unable to re-run") + + LVS::execute_lvs(macro, self.generator("script" => script), params["l2ndb_index"]) + + end + + end - # Register the new interpreters - LVSInterpreter::new - LVSPlainTextInterpreter::new + # Register the recipe + lvs_recipe = LVSRecipe::new + # Register the new interpreters + LVSInterpreter::new(lvs_recipe) + LVSPlainTextInterpreter::new(lvs_recipe) + end diff --git a/src/lvs/unit_tests/lvsSimpleTests.cc b/src/lvs/unit_tests/lvsSimpleTests.cc index 5c3319b22..2fa9252d2 100644 --- a/src/lvs/unit_tests/lvsSimpleTests.cc +++ b/src/lvs/unit_tests/lvsSimpleTests.cc @@ -28,7 +28,7 @@ #include "lymMacro.h" #include "tlFileUtils.h" -void run_test (tl::TestBase *_this, const std::string &suffix, const std::string &layout, bool with_l2n = false) +void run_test (tl::TestBase *_this, const std::string &suffix, const std::string &layout, bool with_l2n = false, const std::string &top = std::string ()) { std::string rs = tl::testsrc (); rs += "/testdata/lvs/" + suffix + ".lvs"; @@ -57,7 +57,8 @@ void run_test (tl::TestBase *_this, const std::string &suffix, const std::string "$lvs_test_target_lvsdb = '%s'\n" "$lvs_test_target_cir = '%s'\n" "$lvs_test_target_l2n = '%s'\n" - , src, output_lvsdb, output_cir, output_l2n) + "$lvs_test_top = '%s'\n" + , src, output_lvsdb, output_cir, output_l2n, top) ); config.set_interpreter (lym::Macro::Ruby); EXPECT_EQ (config.run (), 0); @@ -129,3 +130,27 @@ TEST(11_device_scaling) run_test (_this, "ringo_simple_device_scaling", "ringo.gds"); } +TEST(12_simple_dmos) +{ + run_test (_this, "ringo_simple_dmos", "ringo.gds"); +} + +TEST(13_simple_ringo_device_subcircuits) +{ + run_test (_this, "ringo_device_subcircuits", "ringo.gds"); +} + +TEST(14_simple_ringo_mixed_hierarchy) +{ + run_test (_this, "ringo_mixed_hierarchy", "ringo_mixed_hierarchy.gds"); +} + +TEST(15_simple_dummy_device) +{ + run_test (_this, "ringo_simple_dummy_device", "ringo_dummy_device.gds"); +} + +TEST(16_floating) +{ + run_test (_this, "floating", "floating.gds", false, "TOP"); +} diff --git a/src/lym/lym/gsiDeclLymMacro.cc b/src/lym/lym/gsiDeclLymMacro.cc index bf2bd56b7..6416bba2a 100644 --- a/src/lym/lym/gsiDeclLymMacro.cc +++ b/src/lym/lym/gsiDeclLymMacro.cc @@ -73,9 +73,8 @@ public: }; Class decl_MacroExecutionContext ("lay", "MacroExecutionContext", - gsi::method ("set_debugger_scope", &gsi::MacroExecutionContext::set_debugger_scope, + gsi::method ("set_debugger_scope", &gsi::MacroExecutionContext::set_debugger_scope, gsi::arg ("filename"), "@brief Sets a debugger scope (file level which shall appear in the debugger)\n" - "@args filename\n" "If a debugger scope is set, back traces will be produced starting from that scope. " "Setting a scope is useful for implementing DSL interpreters and giving a proper hint about " "the original location of an error." @@ -277,9 +276,8 @@ Class decl_MacroInterpreter ("lay", "MacroInterpreter", gsi::method ("NoDebugger", &const_NoDebugger, "@brief Indicates no debugging for \\debugger_scheme\n" ) + - gsi::method ("register", &MacroInterpreter::register_gsi, + gsi::method ("register", &MacroInterpreter::register_gsi, gsi::arg ("name"), "@brief Registers the macro interpreter\n" - "@args name\n" "@param name The interpreter name. This is an arbitrary string which should be unique.\n" "\n" "Registration of the interpreter makes the object known to the system. After registration, macros whose interpreter " @@ -351,9 +349,8 @@ Class decl_MacroInterpreter ("lay", "MacroInterpreter", "Before version 0.25 this attribute was a reimplementable method. It has been turned into an attribute for " "performance reasons in version 0.25.\n" ) + - gsi::callback ("execute", &gsi::MacroInterpreter::execute, &gsi::MacroInterpreter::f_execute, + gsi::callback ("execute", &gsi::MacroInterpreter::execute, &gsi::MacroInterpreter::f_execute, gsi::arg ("macro"), "@brief Gets called to execute a macro\n" - "@args macro\n" "This method must be reimplemented to execute the macro. " "The system will call this script when a macro with interpreter type 'dsl' and the " "name of this interpreter is run." @@ -424,6 +421,11 @@ Class decl_MacroInterpreter ("lay", "MacroInterpreter", "This class has been introduced in version 0.23.\n" ); +static lym::Macro *macro_by_path (const std::string &path) +{ + return lym::MacroCollection::root ().find_macro (path); +} + Class decl_Macro ("lay", "Macro", gsi::method ("path", &lym::Macro::path, "@brief Gets the path of the macro\n" @@ -431,6 +433,13 @@ Class decl_Macro ("lay", "Macro", "The path is the path where the macro is stored, starting with an abstract group identifier. " "The path is used to identify the macro in the debugger for example." ) + + gsi::method ("macro_by_path", ¯o_by_path, gsi::arg ("path"), + "@brief Finds the macro by installation path\n" + "\n" + "Returns nil if no macro with this path can be found.\n" + "\n" + "This method has been added in version 0.26." + ) + gsi::method ("name", &lym::Macro::name, "@brief Gets the name of the macro\n" "\n" @@ -443,9 +452,8 @@ Class decl_Macro ("lay", "Macro", "the description text can have the format \"Group;;Description\". In that case, the macro " "will appear in a group with title \"Group\"." ) + - gsi::method ("description=", &lym::Macro::set_description, + gsi::method ("description=", &lym::Macro::set_description, gsi::arg ("description"), "@brief Sets the description text\n" - "@args description\n" "@param description The description text.\n" "See \\description for details.\n" ) + @@ -455,9 +463,8 @@ Class decl_Macro ("lay", "Macro", "The prolog is executed before the actual code is executed. Interpretation depends on the " "implementation of the DSL interpreter for DSL macros." ) + - gsi::method ("prolog=", &lym::Macro::set_prolog, + gsi::method ("prolog=", &lym::Macro::set_prolog, gsi::arg ("string"), "@brief Sets the prolog\n" - "@args string\n" "See \\prolog for details.\n" ) + gsi::method ("epilog", &lym::Macro::epilog, @@ -466,9 +473,8 @@ Class decl_Macro ("lay", "Macro", "The epilog is executed after the actual code is executed. Interpretation depends on the " "implementation of the DSL interpreter for DSL macros." ) + - gsi::method ("epilog=", &lym::Macro::set_epilog, + gsi::method ("epilog=", &lym::Macro::set_epilog, gsi::arg ("string"), "@brief Sets the epilog\n" - "@args string\n" "See \\epilog for details.\n" ) + gsi::method ("category", &lym::Macro::category, @@ -477,9 +483,8 @@ Class decl_Macro ("lay", "Macro", "The category tags string indicates to which categories a macro will belong to. This string " "is only used for templates currently and is a comma-separated list of category names." ) + - gsi::method ("category=", &lym::Macro::set_category, + gsi::method ("category=", &lym::Macro::set_category, gsi::arg ("string"), "@brief Sets the category tags string\n" - "@args string\n" "See \\category for details.\n" ) + gsi::method ("text", &lym::Macro::text, @@ -488,17 +493,15 @@ Class decl_Macro ("lay", "Macro", "The text is the code executed by the macro interpreter. " "Depending on the DSL interpreter, the text can be any kind of code." ) + - gsi::method ("text=", &lym::Macro::set_text, + gsi::method ("text=", &lym::Macro::set_text, gsi::arg ("string"), "@brief Sets the macro text\n" - "@args string\n" "See \\text for details.\n" ) + gsi::method ("show_in_menu?", &lym::Macro::show_in_menu, "@brief Gets a value indicating whether the macro shall be shown in the menu\n" ) + - gsi::method ("show_in_menu=", &lym::Macro::set_show_in_menu, + gsi::method ("show_in_menu=", &lym::Macro::set_show_in_menu, gsi::arg ("flag"), "@brief Sets a value indicating whether the macro shall be shown in the menu\n" - "@args flag\n" ) + gsi::method ("group_name", &lym::Macro::group_name, "@brief Gets the menu group name\n" @@ -506,9 +509,8 @@ Class decl_Macro ("lay", "Macro", "If a group name is specified and \\show_in_menu? is true, the macro will appear in " "a separate group (separated by a separator) together with other macros sharing the same group." ) + - gsi::method ("group_name=", &lym::Macro::set_group_name, + gsi::method ("group_name=", &lym::Macro::set_group_name, gsi::arg ("string"), "@brief Sets the menu group name\n" - "@args string\n" "See \\group_name for details.\n" ) + gsi::method ("menu_path", &lym::Macro::menu_path, @@ -517,9 +519,8 @@ Class decl_Macro ("lay", "Macro", "If a menu path is specified and \\show_in_menu? is true, the macro will appear in " "the menu at the specified position." ) + - gsi::method ("menu_path=", &lym::Macro::set_menu_path, + gsi::method ("menu_path=", &lym::Macro::set_menu_path, gsi::arg ("string"), "@brief Sets the menu path\n" - "@args string\n" "See \\menu_path for details.\n" ), "@brief A macro class\n" diff --git a/src/rba/rba/rbaMarshal.cc b/src/rba/rba/rbaMarshal.cc index 7b0b0d9ad..df03434fe 100644 --- a/src/rba/rba/rbaMarshal.cc +++ b/src/rba/rba/rbaMarshal.cc @@ -350,8 +350,14 @@ struct writer aa->write ((void *)0); } } else { + + if (TYPE (arg) != T_ARRAY) { + throw tl::Exception (tl::sprintf (tl::to_string (tr ("Unexpected object type (expected array, got %s)")), rba_class_name (arg).c_str ())); + } + tl_assert (atype.inner () != 0); aa->write ((void *)new RubyBasedVectorAdaptor (arg, atype.inner ())); + } } }; @@ -370,10 +376,17 @@ struct writer } else { aa->write ((void *)0); } + } else { + + if (TYPE (arg) != T_HASH) { + throw tl::Exception (tl::sprintf (tl::to_string (tr ("Unexpected object type (expected hash, got %s)")), rba_class_name (arg).c_str ())); + } + tl_assert (atype.inner () != 0); tl_assert (atype.inner_k () != 0); aa->write ((void *)new RubyBasedMapAdaptor (arg, atype.inner (), atype.inner_k ())); + } } }; diff --git a/src/tl/tl/tl.pro b/src/tl/tl/tl.pro index b481592d9..39184f182 100644 --- a/src/tl/tl/tl.pro +++ b/src/tl/tl/tl.pro @@ -45,7 +45,8 @@ SOURCES = \ tlUniqueId.cc \ tlList.cc \ tlEquivalenceClusters.cc \ - tlUniqueName.cc + tlUniqueName.cc \ + tlRecipe.cc HEADERS = \ tlAlgorithm.h \ @@ -100,7 +101,8 @@ HEADERS = \ tlUniqueId.h \ tlList.h \ tlEquivalenceClusters.h \ - tlUniqueName.h + tlUniqueName.h \ + tlRecipe.h equals(HAVE_CURL, "1") { diff --git a/src/tl/tl/tlRecipe.cc b/src/tl/tl/tlRecipe.cc new file mode 100644 index 000000000..157280a32 --- /dev/null +++ b/src/tl/tl/tlRecipe.cc @@ -0,0 +1,91 @@ + +/* + + KLayout Layout Viewer + Copyright (C) 2006-2019 Matthias Koefferlein + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +*/ + +#include "tlRecipe.h" +#include "tlString.h" + +namespace tl +{ + +Recipe::Recipe (const std::string &name, const std::string &description) + : tl::RegisteredClass (this, 0, name.c_str (), false) +{ + m_name = name; + m_description = description; +} + +std::string Recipe::generator (const std::map ¶ms) +{ + std::string g; + g += tl::to_word_or_quoted_string (name ()); + g += ": "; + + for (std::map::const_iterator p = params.begin (); p != params.end (); ++p) { + if (p != params.begin ()) { + g += ","; + } + g += tl::to_word_or_quoted_string (p->first); + g += "="; + g += p->second.to_parsable_string (); + } + + return g; +} + +tl::Variant Recipe::make (const std::string &generator, const std::map &padd) +{ + tl::Extractor ex (generator.c_str ()); + + std::string recipe; + ex.read_word_or_quoted (recipe); + ex.test (":"); + + std::map params; + while (! ex.at_end ()) { + std::string key; + ex.read_word_or_quoted (key); + ex.test ("="); + tl::Variant v; + ex.read (v); + ex.test (","); + params.insert (std::make_pair (key, v)); + } + + for (std::map::const_iterator p = padd.begin (); p != padd.end (); ++p) { + params.insert (*p); + } + + tl::Recipe *recipe_obj = 0; + for (tl::Registrar::iterator r = tl::Registrar::begin (); r != tl::Registrar::end (); ++r) { + if (r->name () == recipe) { + recipe_obj = r.operator-> (); + } + } + + if (! recipe_obj) { + return tl::Variant (); + } else { + return recipe_obj->execute (params); + } +} + +} // namespace tl diff --git a/src/tl/tl/tlRecipe.h b/src/tl/tl/tlRecipe.h new file mode 100644 index 000000000..900b48ed1 --- /dev/null +++ b/src/tl/tl/tlRecipe.h @@ -0,0 +1,134 @@ + +/* + + KLayout Layout Viewer + Copyright (C) 2006-2019 Matthias Koefferlein + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +*/ + + +#ifndef HDR_tlRecipe +#define HDR_tlRecipe + +#include "tlCommon.h" +#include "tlVariant.h" +#include "tlTypeTraits.h" +#include "tlClassRegistry.h" + +namespace tl +{ + +/** + * @brief A facility for providing reproducable recipes + * + * The idea of this facility is to provide a service by which an object + * can be reproduced in a parametrized way. The intended use case is a + * DRC report for example, where the DRC script is the generator. + * + * In this use case, the DRC engine will register a recipe. It will + * put the serialized version of the recipe into the DRC report. If the + * user requests a re-run of the DRC, the recipe will be called and + * the implementation is supposed to deliver a new database. + * + * To register a recipe, reimplement tl::Recipe and create a singleton + * instance. To serialize a recipe, use "generator", to execute the + * recipe, use "make". + * + * Parameters are kept as a generic key/value map. + */ +class TL_PUBLIC Recipe + : public tl::RegisteredClass +{ +public: + /** + * @brief @brief Creates a new recipe object + */ + Recipe (const std::string &name, const std::string &description = std::string ()); + + /** + * @brief Destructor + */ + virtual ~Recipe () { } + + /** + * @brief Gets the recipes name (a unique identifier) + */ + const std::string &name () const + { + return m_name; + } + + /** + * @brief Gets the description text + */ + const std::string &description () const + { + return m_description; + } + + /** + * @brief An utility function to get a parameters + */ + template + static T get_value (const std::map ¶ms, const std::string &pname, const T &def_value) + { + std::map::const_iterator p = params.find (pname); + if (p != params.end ()) { + const tl::Variant &v = p->second; + return v.to (); + } else { + return def_value; + } + } + + /** + * @brief Serializes the given recipe + */ + std::string generator (const std::map ¶ms); + + /** + * @brief Executes the recipe from the generator + * + * Returns nil if the recipe can't be executed, e.g. because the recipe isn't known. + * Additional parameters can be passed in the second argument. + * They have lower priority than the parameters kept in the generator argument. + */ + static tl::Variant make (const std::string &generator, const std::map ¶ms = std::map ()); + + /** + * @brief Recipe interface: executes the recipe with the given parameters + */ + virtual tl::Variant execute (const std::map ¶ms) const = 0; + +private: + Recipe (const Recipe &) : tl::RegisteredClass (this) { } + Recipe &operator= (const Recipe &) { return *this; } + + std::string m_name; + std::string m_description; +}; + +template<> struct type_traits : public type_traits +{ + typedef tl::false_tag has_copy_constructor; + typedef tl::false_tag has_default_constructor; +}; + +} // namespace tl + +#endif + diff --git a/src/tl/unit_tests/tlRecipeTests.cc b/src/tl/unit_tests/tlRecipeTests.cc new file mode 100644 index 000000000..21bbc3f50 --- /dev/null +++ b/src/tl/unit_tests/tlRecipeTests.cc @@ -0,0 +1,64 @@ + +/* + + KLayout Layout Viewer + Copyright (C) 2006-2019 Matthias Koefferlein + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +*/ + +#include "tlRecipe.h" +#include "tlUnitTest.h" + +#include + +namespace { + + class MyRecipe : public tl::Recipe + { + public: + MyRecipe () : tl::Recipe ("test_recipe", "description") { } + + tl::Variant execute (const std::map ¶ms) const + { + int a = get_value (params, "A", 0); + double b = get_value (params, "B", 0.0); + double c = get_value (params, "C", 1.0); + return tl::Variant (b * a * c); + } + }; + + static MyRecipe my_recipe; + +} + +// basic abilities +TEST(1) +{ + std::map params; + params["A"] = tl::Variant (7); + params["B"] = tl::Variant (6.0); + std::string g = my_recipe.generator (params); + EXPECT_EQ (g, "test_recipe: A=#7,B=##6"); + + tl::Variant res = tl::Recipe::make (g); + EXPECT_EQ (res.to_double (), 42.0); + + std::map padd; + padd["C"] = tl::Variant(1.5); + res = tl::Recipe::make (g, padd); + EXPECT_EQ (res.to_double (), 63.0); +} diff --git a/src/tl/unit_tests/unit_tests.pro b/src/tl/unit_tests/unit_tests.pro index 092699eef..989902872 100644 --- a/src/tl/unit_tests/unit_tests.pro +++ b/src/tl/unit_tests/unit_tests.pro @@ -38,7 +38,8 @@ SOURCES = \ tlListTests.cc \ tlEquivalenceClustersTests.cc \ tlUniqueNameTests.cc \ - tlGlobPatternTests.cc + tlGlobPatternTests.cc \ + tlRecipeTests.cc !equals(HAVE_QT, "0") { diff --git a/testdata/algo/device_extract_au9.gds b/testdata/algo/device_extract_au9.gds new file mode 100644 index 000000000..f8c19fbd8 Binary files /dev/null and b/testdata/algo/device_extract_au9.gds differ diff --git a/testdata/algo/device_extract_l9.gds b/testdata/algo/device_extract_l9.gds new file mode 100644 index 000000000..675834219 Binary files /dev/null and b/testdata/algo/device_extract_l9.gds differ diff --git a/testdata/algo/l2n_writer_au_2.txt b/testdata/algo/l2n_reader_au.txt similarity index 100% rename from testdata/algo/l2n_writer_au_2.txt rename to testdata/algo/l2n_reader_au.txt diff --git a/testdata/algo/l2n_reader_au_1.gds b/testdata/algo/l2n_reader_au_1.gds index 95598a9d6..2b85b42ac 100644 Binary files a/testdata/algo/l2n_reader_au_1.gds and b/testdata/algo/l2n_reader_au_1.gds differ diff --git a/testdata/algo/l2n_reader_au_2.gds b/testdata/algo/l2n_reader_au_2.gds index 100f1aee7..ffae4bd90 100644 Binary files a/testdata/algo/l2n_reader_au_2.gds and b/testdata/algo/l2n_reader_au_2.gds differ diff --git a/testdata/algo/l2n_reader_au_2r.gds b/testdata/algo/l2n_reader_au_2r.gds new file mode 100644 index 000000000..70dbdd3de Binary files /dev/null and b/testdata/algo/l2n_reader_au_2r.gds differ diff --git a/testdata/algo/l2n_writer_au_2_abs.txt b/testdata/algo/l2n_reader_au_abs.txt similarity index 100% rename from testdata/algo/l2n_writer_au_2_abs.txt rename to testdata/algo/l2n_reader_au_abs.txt diff --git a/testdata/algo/l2n_writer_au.txt b/testdata/algo/l2n_writer_au.txt index 6a9228b28..3d97644d3 100644 --- a/testdata/algo/l2n_writer_au.txt +++ b/testdata/algo/l2n_writer_au.txt @@ -363,54 +363,108 @@ circuit(RINGO rect(metal2_lbl (-23941 -381) (2 2)) ) net(5 + rect(diff_cont (20210 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(6 + rect(diff_cont (17570 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(7 + rect(diff_cont (14930 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(8 + rect(diff_cont (12290 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(9 + rect(diff_cont (9650 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(10 + rect(diff_cont (7010 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(11 + rect(diff_cont (4370 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(12 + rect(diff_cont (1730 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(13 + rect(diff_cont (-910 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(14 rect(diff_cont (690 2890) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -2620) (220 220)) rect(diff_cont (-220 -620) (220 220)) ) - net(6 + net(15 rect(diff_cont (21810 2890) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -2620) (220 220)) rect(diff_cont (-220 -620) (220 220)) ) - net(7 + net(16 rect(diff_cont (19170 2890) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -2620) (220 220)) rect(diff_cont (-220 -620) (220 220)) ) - net(8 + net(17 rect(diff_cont (16530 2890) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -2620) (220 220)) rect(diff_cont (-220 -620) (220 220)) ) - net(9 + net(18 rect(diff_cont (13890 2890) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -2620) (220 220)) rect(diff_cont (-220 -620) (220 220)) ) - net(10 + net(19 rect(diff_cont (11250 2890) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -2620) (220 220)) rect(diff_cont (-220 -620) (220 220)) ) - net(11 + net(20 rect(diff_cont (8610 2890) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -2620) (220 220)) rect(diff_cont (-220 -620) (220 220)) ) - net(12 + net(21 rect(diff_cont (5970 2890) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -2620) (220 220)) rect(diff_cont (-220 -620) (220 220)) ) - net(13 + net(22 rect(diff_cont (3330 2890) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -2620) (220 220)) @@ -425,7 +479,7 @@ circuit(RINGO # Subcircuits and their connections circuit(1 INV2 location(23760 0) - pin(0 6) + pin(0 15) pin(1 1) pin(2 2) pin(3 3) @@ -433,55 +487,64 @@ circuit(RINGO ) circuit(2 INV2 location(0 0) pin(0 1) - pin(2 5) + pin(1 13) + pin(2 14) pin(3 3) pin(4 4) ) circuit(3 INV2 location(2640 0) - pin(0 5) - pin(2 13) + pin(0 14) + pin(1 12) + pin(2 22) pin(3 3) pin(4 4) ) circuit(4 INV2 location(5280 0) - pin(0 13) - pin(2 12) + pin(0 22) + pin(1 11) + pin(2 21) pin(3 3) pin(4 4) ) circuit(5 INV2 location(7920 0) - pin(0 12) - pin(2 11) + pin(0 21) + pin(1 10) + pin(2 20) pin(3 3) pin(4 4) ) circuit(6 INV2 location(10560 0) - pin(0 11) - pin(2 10) + pin(0 20) + pin(1 9) + pin(2 19) pin(3 3) pin(4 4) ) circuit(7 INV2 location(13200 0) - pin(0 10) - pin(2 9) + pin(0 19) + pin(1 8) + pin(2 18) pin(3 3) pin(4 4) ) circuit(8 INV2 location(15840 0) - pin(0 9) - pin(2 8) + pin(0 18) + pin(1 7) + pin(2 17) pin(3 3) pin(4 4) ) circuit(9 INV2 location(18480 0) - pin(0 8) - pin(2 7) + pin(0 17) + pin(1 6) + pin(2 16) pin(3 3) pin(4 4) ) circuit(10 INV2 location(21120 0) - pin(0 7) - pin(2 6) + pin(0 16) + pin(1 5) + pin(2 15) pin(3 3) pin(4 4) ) diff --git a/testdata/algo/l2n_writer_au_2.gds b/testdata/algo/l2n_writer_au_2.gds index 6ba0a3c82..ad232c888 100644 Binary files a/testdata/algo/l2n_writer_au_2.gds and b/testdata/algo/l2n_writer_au_2.gds differ diff --git a/testdata/algo/l2n_writer_au_2b.txt b/testdata/algo/l2n_writer_au_2b.txt new file mode 100644 index 000000000..c232887a5 --- /dev/null +++ b/testdata/algo/l2n_writer_au_2b.txt @@ -0,0 +1,619 @@ +#%l2n-klayout +top(RINGO) +unit(0.001) + +# Layer section +# This section lists the mask layers (drawing or derived) and their connections. + +# Mask layers +layer(rbulk) +layer(nwell '1/0') +layer(poly '3/0') +layer(poly_lbl '3/1') +layer(diff_cont '4/0') +layer(poly_cont '5/0') +layer(metal1 '6/0') +layer(metal1_lbl '6/1') +layer(via1 '7/0') +layer(metal2 '8/0') +layer(metal2_lbl '8/1') +layer(ntie) +layer(psd) +layer(ptie) +layer(nsd) + +# Mask layer connectivity +connect(nwell nwell ntie) +connect(poly poly poly_lbl poly_cont) +connect(poly_lbl poly) +connect(diff_cont diff_cont metal1 ntie psd ptie nsd) +connect(poly_cont poly poly_cont metal1) +connect(metal1 diff_cont poly_cont metal1 metal1_lbl via1) +connect(metal1_lbl metal1) +connect(via1 metal1 via1 metal2) +connect(metal2 via1 metal2 metal2_lbl) +connect(metal2_lbl metal2) +connect(ntie nwell diff_cont ntie) +connect(psd diff_cont psd) +connect(ptie diff_cont ptie) +connect(nsd diff_cont nsd) + +# Global nets and connectivity +global(rbulk BULK) +global(ptie BULK) + +# Device class section +class(PMOS MOS4) +class(NMOS MOS4) + +# Device abstracts section +# Device abstracts list the pin shapes of the devices. +device(D$PMOS PMOS + terminal(S + rect(psd (-650 -475) (525 950)) + ) + terminal(G + rect(poly (-125 -475) (250 950)) + ) + terminal(D + rect(psd (125 -475) (550 950)) + ) + terminal(B + rect(nwell (-125 -475) (250 950)) + ) +) +device(D$PMOS$1 PMOS + terminal(S + rect(psd (-675 -475) (550 950)) + ) + terminal(G + rect(poly (-125 -475) (250 950)) + ) + terminal(D + rect(psd (125 -475) (525 950)) + ) + terminal(B + rect(nwell (-125 -475) (250 950)) + ) +) +device(D$NMOS NMOS + terminal(S + rect(nsd (-650 -475) (525 950)) + ) + terminal(G + rect(poly (-125 -475) (250 950)) + ) + terminal(D + rect(nsd (125 -475) (550 950)) + ) + terminal(B + rect(rbulk (-125 -475) (250 950)) + ) +) +device(D$NMOS$1 NMOS + terminal(S + rect(nsd (-675 -475) (550 950)) + ) + terminal(G + rect(poly (-125 -475) (250 950)) + ) + terminal(D + rect(nsd (125 -475) (525 950)) + ) + terminal(B + rect(rbulk (-125 -475) (250 950)) + ) +) + +# Circuit section +# Circuits are the hierarchical building blocks of the netlist. +circuit(INV2 + + # Circuit boundary + rect((-1700 -1640) (3100 6220)) + + # Nets with their geometries + net(1 + rect(nwell (-1400 1800) (2800 2780)) + rect(diff_cont (-1510 -650) (220 220)) + rect(ntie (-510 -450) (800 680)) + ) + net(2 name(IN) + rect(poly (-525 -250) (250 2500)) + rect(poly (-1425 -630) (1300 360)) + rect(poly (-125 -2780) (250 1600)) + rect(poly (-250 1200) (250 1600)) + rect(poly_lbl (-526 -1801) (2 2)) + rect(poly_cont (-831 -111) (220 220)) + ) + net(3 + rect(poly (275 -250) (250 2500)) + rect(poly (-305 -1430) (360 360)) + rect(poly (-305 820) (250 1600)) + rect(poly (-250 -4400) (250 1600)) + rect(diff_cont (-1435 1690) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(poly_cont (980 580) (220 220)) + rect(metal1 (-1310 -290) (1380 360)) + rect(metal1 (-1560 -1600) (360 2840)) + rect(metal1 (-360 0) (360 760)) + rect(metal1 (-360 -3560) (360 760)) + rect(psd (-430 1945) (525 950)) + rect(nsd (-525 -3750) (525 950)) + ) + net(4 name(OUT) + rect(diff_cont (690 2890) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -2620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + polygon(metal1 (-110 110) (0 360) (140 0) (0 1240) (-320 0) (0 800) (360 0) (0 -440) (320 0) (0 -1960)) + rect(metal1 (-680 2400) (360 760)) + rect(metal1 (-360 -3560) (360 760)) + rect(metal1_lbl (-181 1419) (2 2)) + rect(psd (-276 524) (525 950)) + rect(nsd (-525 -3750) (525 950)) + ) + net(5 name(VSS) + rect(diff_cont (-110 -310) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(metal1 (-290 -290) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(via1 (-305 -705) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(metal2 (-1525 -775) (2800 900)) + rect(metal2_lbl (-161 -541) (2 2)) + rect(nsd (-1516 -386) (550 950)) + ) + net(6 name(VDD) + rect(diff_cont (-110 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(metal1 (-290 -290) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(via1 (-305 -705) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(metal2 (-1525 -775) (2800 900)) + rect(metal2_lbl (-151 -451) (2 2)) + rect(psd (-1526 -476) (550 950)) + ) + net(7 name(BULK) + rect(diff_cont (-110 -1360) (220 220)) + rect(ptie (-510 -450) (800 680)) + ) + + # Outgoing pins and their connections to nets + pin(1) + pin(2 name(IN)) + pin(3) + pin(4 name(OUT)) + pin(5 name(VSS)) + pin(6 name(VDD)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 D$PMOS + location(-400 2800) + param(L 0.25) + param(W 0.95) + param(AS 0.49875) + param(AD 0.26125) + param(PS 2.95) + param(PD 1.5) + terminal(S 3) + terminal(G 2) + terminal(D 6) + terminal(B 1) + ) + device(2 D$PMOS$1 + location(400 2800) + param(L 0.25) + param(W 0.95) + param(AS 0.26125) + param(AD 0.49875) + param(PS 1.5) + param(PD 2.95) + terminal(S 6) + terminal(G 3) + terminal(D 4) + terminal(B 1) + ) + device(3 D$NMOS + location(-400 0) + param(L 0.25) + param(W 0.95) + param(AS 0.49875) + param(AD 0.26125) + param(PS 2.95) + param(PD 1.5) + terminal(S 3) + terminal(G 2) + terminal(D 5) + terminal(B 7) + ) + device(4 D$NMOS$1 + location(400 0) + param(L 0.25) + param(W 0.95) + param(AS 0.26125) + param(AD 0.49875) + param(PS 1.5) + param(PD 2.95) + terminal(S 5) + terminal(G 3) + terminal(D 4) + terminal(B 7) + ) + +) +circuit(INV2PAIR + + # Circuit boundary + rect((0 -840) (5740 6220)) + + # Nets with their geometries + net(1 name(BULK)) + net(2 + rect(diff_cont (3430 3290) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(3 + rect(diff_cont (790 3290) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(4 + rect(diff_cont (4230 3290) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-2860 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(metal1 (2350 -290) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (-3000 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + ) + net(5 + rect(diff_cont (4230 490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-2860 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(metal1 (2350 -290) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (-3000 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + ) + net(6 + rect(diff_cont (2390 3690) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -2620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + ) + net(7) + net(8 + rect(diff_cont (5030 3690) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -2620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + ) + net(9) + + # Outgoing pins and their connections to nets + pin(1 name(BULK)) + pin(2) + pin(4) + pin(5) + pin(7) + pin(8) + pin(9) + + # Subcircuits and their connections + circuit(1 INV2 location(1700 800) + pin(0 9) + pin(1 7) + pin(2 3) + pin(3 6) + pin(4 5) + pin(5 4) + pin(6 1) + ) + circuit(2 INV2 location(4340 800) + pin(0 9) + pin(1 6) + pin(2 2) + pin(3 8) + pin(4 5) + pin(5 4) + pin(6 1) + ) + +) +circuit(RINGO + + # Circuit boundary + rect((-1720 -1640) (26880 6220)) + + # Nets with their geometries + net(1 name(FB) + rect(diff_cont (22850 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(metal1 (-24770 1310) (360 360)) + rect(via1 (-305 -305) (250 250)) + rect(via1 (24230 -250) (250 250)) + rect(metal2 (-24805 -325) (24880 400)) + rect(metal2_lbl (-23161 -201) (2 2)) + ) + net(2 name(OSC) + rect(diff_cont (24450 2890) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -2620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(via1 (-235 1765) (250 250)) + rect(metal2 (-325 -325) (400 400)) + rect(metal2_lbl (-201 -201) (2 2)) + ) + net(3 name(VDD) + rect(diff_cont (7810 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-2860 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-2860 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-2860 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (12980 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-2860 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (7700 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-2860 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (7700 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-2860 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(metal1 (-21410 390) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (-16200 -1800) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (-3000 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (-3000 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (-3000 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (12840 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (-3000 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (7560 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (-3000 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (7560 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (-3000 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal2_lbl (-21301 -381) (2 2)) + ) + net(4 name(VSS) + rect(diff_cont (7810 -310) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-2860 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-2860 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-2860 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (12980 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-2860 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (7700 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-2860 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (7700 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-2860 -220) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -220) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(metal1 (-21410 -1330) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (-16200 -80) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (-3000 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (-3000 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (-3000 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (12840 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (-3000 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (7560 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (-3000 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (7560 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal1 (-3000 -760) (360 760)) + rect(metal1 (-360 -760) (360 760)) + rect(metal2_lbl (-21301 -381) (2 2)) + ) + net(5 + rect(diff_cont (17570 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(6 + rect(diff_cont (12290 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(7 + rect(diff_cont (7010 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(8 + rect(diff_cont (1730 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(9 + rect(diff_cont (3330 2890) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -2620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + ) + net(10 + rect(diff_cont (19170 2890) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -2620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + ) + net(11 + rect(diff_cont (13890 2890) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -2620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + ) + net(12 + rect(diff_cont (8610 2890) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -2620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(FB)) + pin(2 name(OSC)) + pin(3 name(VDD)) + pin(4 name(VSS)) + + # Subcircuits and their connections + circuit(1 INV2PAIR location(19420 -800) + pin(0 4) + pin(1 1) + pin(2 3) + pin(3 4) + pin(4 10) + pin(5 2) + pin(6 3) + ) + circuit(2 INV2PAIR location(-1700 -800) + pin(0 4) + pin(1 8) + pin(2 3) + pin(3 4) + pin(4 1) + pin(5 9) + pin(6 3) + ) + circuit(3 INV2PAIR location(3580 -800) + pin(0 4) + pin(1 7) + pin(2 3) + pin(3 4) + pin(4 9) + pin(5 12) + pin(6 3) + ) + circuit(4 INV2PAIR location(8860 -800) + pin(0 4) + pin(1 6) + pin(2 3) + pin(3 4) + pin(4 12) + pin(5 11) + pin(6 3) + ) + circuit(5 INV2PAIR location(14140 -800) + pin(0 4) + pin(1 5) + pin(2 3) + pin(3 4) + pin(4 11) + pin(5 10) + pin(6 3) + ) + +) diff --git a/testdata/algo/l2n_writer_au_2s.txt b/testdata/algo/l2n_writer_au_2s.txt index 7af0f364f..c12295b2d 100644 --- a/testdata/algo/l2n_writer_au_2s.txt +++ b/testdata/algo/l2n_writer_au_2s.txt @@ -232,6 +232,12 @@ X(INV2PAIR R(diff_cont (-220 180) (220 220)) ) N(3 + R(diff_cont (790 3290) (220 220)) + R(diff_cont (-220 180) (220 220)) + R(diff_cont (-220 -3420) (220 220)) + R(diff_cont (-220 180) (220 220)) + ) + N(4 R(diff_cont (4230 3290) (220 220)) R(diff_cont (-220 180) (220 220)) R(diff_cont (-220 -220) (220 220)) @@ -245,7 +251,7 @@ X(INV2PAIR R(metal1 (-3000 -760) (360 760)) R(metal1 (-360 -760) (360 760)) ) - N(4 + N(5 R(diff_cont (4230 490) (220 220)) R(diff_cont (-220 180) (220 220)) R(diff_cont (-220 -220) (220 220)) @@ -259,42 +265,43 @@ X(INV2PAIR R(metal1 (-3000 -760) (360 760)) R(metal1 (-360 -760) (360 760)) ) - N(5 + N(6 R(diff_cont (2390 3690) (220 220)) R(diff_cont (-220 -620) (220 220)) R(diff_cont (-220 -2620) (220 220)) R(diff_cont (-220 -620) (220 220)) ) - N(6) - N(7 + N(7) + N(8 R(diff_cont (5030 3690) (220 220)) R(diff_cont (-220 -620) (220 220)) R(diff_cont (-220 -2620) (220 220)) R(diff_cont (-220 -620) (220 220)) ) - N(8) + N(9) P(1 I(BULK)) P(2) - P(3) P(4) - P(6) + P(5) P(7) P(8) + P(9) X(1 INV2 Y(1700 800) - P(0 8) - P(1 6) - P(3 5) - P(4 4) - P(5 3) + P(0 9) + P(1 7) + P(2 3) + P(3 6) + P(4 5) + P(5 4) P(6 1) ) X(2 INV2 Y(4340 800) - P(0 8) - P(1 5) + P(0 9) + P(1 6) P(2 2) - P(3 7) - P(4 4) - P(5 3) + P(3 8) + P(4 5) + P(5 4) P(6 1) ) ) @@ -467,24 +474,48 @@ X(RINGO R(metal2_lbl (-21301 -381) (2 2)) ) N(5 + R(diff_cont (17570 2490) (220 220)) + R(diff_cont (-220 180) (220 220)) + R(diff_cont (-220 -3420) (220 220)) + R(diff_cont (-220 180) (220 220)) + ) + N(6 + R(diff_cont (12290 2490) (220 220)) + R(diff_cont (-220 180) (220 220)) + R(diff_cont (-220 -3420) (220 220)) + R(diff_cont (-220 180) (220 220)) + ) + N(7 + R(diff_cont (7010 2490) (220 220)) + R(diff_cont (-220 180) (220 220)) + R(diff_cont (-220 -3420) (220 220)) + R(diff_cont (-220 180) (220 220)) + ) + N(8 + R(diff_cont (1730 2490) (220 220)) + R(diff_cont (-220 180) (220 220)) + R(diff_cont (-220 -3420) (220 220)) + R(diff_cont (-220 180) (220 220)) + ) + N(9 R(diff_cont (3330 2890) (220 220)) R(diff_cont (-220 -620) (220 220)) R(diff_cont (-220 -2620) (220 220)) R(diff_cont (-220 -620) (220 220)) ) - N(6 + N(10 R(diff_cont (19170 2890) (220 220)) R(diff_cont (-220 -620) (220 220)) R(diff_cont (-220 -2620) (220 220)) R(diff_cont (-220 -620) (220 220)) ) - N(7 + N(11 R(diff_cont (13890 2890) (220 220)) R(diff_cont (-220 -620) (220 220)) R(diff_cont (-220 -2620) (220 220)) R(diff_cont (-220 -620) (220 220)) ) - N(8 + N(12 R(diff_cont (8610 2890) (220 220)) R(diff_cont (-220 -620) (220 220)) R(diff_cont (-220 -2620) (220 220)) @@ -499,40 +530,44 @@ X(RINGO P(1 1) P(2 3) P(3 4) - P(4 6) + P(4 10) P(5 2) P(6 3) ) X(2 INV2PAIR Y(-1700 -800) P(0 4) + P(1 8) P(2 3) P(3 4) P(4 1) - P(5 5) + P(5 9) P(6 3) ) X(3 INV2PAIR Y(3580 -800) P(0 4) + P(1 7) P(2 3) P(3 4) - P(4 5) - P(5 8) + P(4 9) + P(5 12) P(6 3) ) X(4 INV2PAIR Y(8860 -800) P(0 4) + P(1 6) P(2 3) P(3 4) - P(4 8) - P(5 7) + P(4 12) + P(5 11) P(6 3) ) X(5 INV2PAIR Y(14140 -800) P(0 4) + P(1 5) P(2 3) P(3 4) - P(4 7) - P(5 6) + P(4 11) + P(5 10) P(6 3) ) ) diff --git a/testdata/algo/l2n_writer_au_s.txt b/testdata/algo/l2n_writer_au_s.txt index 84903d827..5d9d02240 100644 --- a/testdata/algo/l2n_writer_au_s.txt +++ b/testdata/algo/l2n_writer_au_s.txt @@ -333,54 +333,108 @@ X(RINGO R(metal2_lbl (-23941 -381) (2 2)) ) N(5 + R(diff_cont (20210 2490) (220 220)) + R(diff_cont (-220 180) (220 220)) + R(diff_cont (-220 -3420) (220 220)) + R(diff_cont (-220 180) (220 220)) + ) + N(6 + R(diff_cont (17570 2490) (220 220)) + R(diff_cont (-220 180) (220 220)) + R(diff_cont (-220 -3420) (220 220)) + R(diff_cont (-220 180) (220 220)) + ) + N(7 + R(diff_cont (14930 2490) (220 220)) + R(diff_cont (-220 180) (220 220)) + R(diff_cont (-220 -3420) (220 220)) + R(diff_cont (-220 180) (220 220)) + ) + N(8 + R(diff_cont (12290 2490) (220 220)) + R(diff_cont (-220 180) (220 220)) + R(diff_cont (-220 -3420) (220 220)) + R(diff_cont (-220 180) (220 220)) + ) + N(9 + R(diff_cont (9650 2490) (220 220)) + R(diff_cont (-220 180) (220 220)) + R(diff_cont (-220 -3420) (220 220)) + R(diff_cont (-220 180) (220 220)) + ) + N(10 + R(diff_cont (7010 2490) (220 220)) + R(diff_cont (-220 180) (220 220)) + R(diff_cont (-220 -3420) (220 220)) + R(diff_cont (-220 180) (220 220)) + ) + N(11 + R(diff_cont (4370 2490) (220 220)) + R(diff_cont (-220 180) (220 220)) + R(diff_cont (-220 -3420) (220 220)) + R(diff_cont (-220 180) (220 220)) + ) + N(12 + R(diff_cont (1730 2490) (220 220)) + R(diff_cont (-220 180) (220 220)) + R(diff_cont (-220 -3420) (220 220)) + R(diff_cont (-220 180) (220 220)) + ) + N(13 + R(diff_cont (-910 2490) (220 220)) + R(diff_cont (-220 180) (220 220)) + R(diff_cont (-220 -3420) (220 220)) + R(diff_cont (-220 180) (220 220)) + ) + N(14 R(diff_cont (690 2890) (220 220)) R(diff_cont (-220 -620) (220 220)) R(diff_cont (-220 -2620) (220 220)) R(diff_cont (-220 -620) (220 220)) ) - N(6 + N(15 R(diff_cont (21810 2890) (220 220)) R(diff_cont (-220 -620) (220 220)) R(diff_cont (-220 -2620) (220 220)) R(diff_cont (-220 -620) (220 220)) ) - N(7 + N(16 R(diff_cont (19170 2890) (220 220)) R(diff_cont (-220 -620) (220 220)) R(diff_cont (-220 -2620) (220 220)) R(diff_cont (-220 -620) (220 220)) ) - N(8 + N(17 R(diff_cont (16530 2890) (220 220)) R(diff_cont (-220 -620) (220 220)) R(diff_cont (-220 -2620) (220 220)) R(diff_cont (-220 -620) (220 220)) ) - N(9 + N(18 R(diff_cont (13890 2890) (220 220)) R(diff_cont (-220 -620) (220 220)) R(diff_cont (-220 -2620) (220 220)) R(diff_cont (-220 -620) (220 220)) ) - N(10 + N(19 R(diff_cont (11250 2890) (220 220)) R(diff_cont (-220 -620) (220 220)) R(diff_cont (-220 -2620) (220 220)) R(diff_cont (-220 -620) (220 220)) ) - N(11 + N(20 R(diff_cont (8610 2890) (220 220)) R(diff_cont (-220 -620) (220 220)) R(diff_cont (-220 -2620) (220 220)) R(diff_cont (-220 -620) (220 220)) ) - N(12 + N(21 R(diff_cont (5970 2890) (220 220)) R(diff_cont (-220 -620) (220 220)) R(diff_cont (-220 -2620) (220 220)) R(diff_cont (-220 -620) (220 220)) ) - N(13 + N(22 R(diff_cont (3330 2890) (220 220)) R(diff_cont (-220 -620) (220 220)) R(diff_cont (-220 -2620) (220 220)) @@ -391,7 +445,7 @@ X(RINGO P(3 I(VSS)) P(4 I(VDD)) X(1 INV2 Y(23760 0) - P(0 6) + P(0 15) P(1 1) P(2 2) P(3 3) @@ -399,55 +453,64 @@ X(RINGO ) X(2 INV2 Y(0 0) P(0 1) - P(2 5) + P(1 13) + P(2 14) P(3 3) P(4 4) ) X(3 INV2 Y(2640 0) - P(0 5) - P(2 13) + P(0 14) + P(1 12) + P(2 22) P(3 3) P(4 4) ) X(4 INV2 Y(5280 0) - P(0 13) - P(2 12) + P(0 22) + P(1 11) + P(2 21) P(3 3) P(4 4) ) X(5 INV2 Y(7920 0) - P(0 12) - P(2 11) + P(0 21) + P(1 10) + P(2 20) P(3 3) P(4 4) ) X(6 INV2 Y(10560 0) - P(0 11) - P(2 10) + P(0 20) + P(1 9) + P(2 19) P(3 3) P(4 4) ) X(7 INV2 Y(13200 0) - P(0 10) - P(2 9) + P(0 19) + P(1 8) + P(2 18) P(3 3) P(4 4) ) X(8 INV2 Y(15840 0) - P(0 9) - P(2 8) + P(0 18) + P(1 7) + P(2 17) P(3 3) P(4 4) ) X(9 INV2 Y(18480 0) - P(0 8) - P(2 7) + P(0 17) + P(1 6) + P(2 16) P(3 3) P(4 4) ) X(10 INV2 Y(21120 0) - P(0 7) - P(2 6) + P(0 16) + P(1 5) + P(2 15) P(3 3) P(4 4) ) diff --git a/testdata/algo/lvs_test1_au.lvsdb.1 b/testdata/algo/lvs_test1_au.lvsdb.1 index 5f45d3819..add09797d 100644 --- a/testdata/algo/lvs_test1_au.lvsdb.1 +++ b/testdata/algo/lvs_test1_au.lvsdb.1 @@ -655,7 +655,7 @@ layout( rect(metal2_lbl (-21301 -381) (2 2)) ) net(5 - rect(diff_cont (1730 90) (220 220)) + rect(diff_cont (14930 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -673,7 +673,7 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(6 - rect(diff_cont (17570 90) (220 220)) + rect(diff_cont (9650 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -691,7 +691,7 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(7 - rect(diff_cont (12290 90) (220 220)) + rect(diff_cont (4370 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -709,6 +709,78 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(8 + rect(diff_cont (-910 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(9 + rect(diff_cont (1730 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(10 + rect(diff_cont (17570 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(11 + rect(diff_cont (12290 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(12 rect(diff_cont (7010 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -739,7 +811,7 @@ layout( pin(1 3) pin(2 4) pin(3 1) - pin(4 6) + pin(4 10) pin(5 2) pin(6 3) ) @@ -747,32 +819,36 @@ layout( pin(0 4) pin(1 3) pin(2 4) + pin(3 8) pin(4 1) - pin(5 5) + pin(5 9) pin(6 3) ) circuit(3 INV2PAIR location(3580 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 5) - pin(5 8) + pin(3 7) + pin(4 9) + pin(5 12) pin(6 3) ) circuit(4 INV2PAIR location(8860 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 8) - pin(5 7) + pin(3 6) + pin(4 12) + pin(5 11) pin(6 3) ) circuit(5 INV2PAIR location(14140 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 7) - pin(5 6) + pin(3 5) + pin(4 11) + pin(5 10) pin(6 3) ) @@ -882,9 +958,13 @@ reference( net(3 name('3')) net(4 name('4')) net(5 name('6')) - net(6 name('5')) - net(7 name('8')) - net(8 name('7')) + net(6 name('100')) + net(7 name('5')) + net(8 name('101')) + net(9 name('8')) + net(10 name('102')) + net(11 name('7')) + net(12 name('103')) # Outgoing pins and their connections to nets pin(1 name('1')) @@ -906,31 +986,35 @@ reference( pin(0 4) pin(1 3) pin(2 4) + pin(3 6) pin(4 1) - pin(5 6) + pin(5 7) pin(6 3) ) circuit(3 INV2PAIR name($3) pin(0 4) pin(1 3) pin(2 4) - pin(4 6) - pin(5 7) + pin(3 8) + pin(4 7) + pin(5 9) pin(6 3) ) circuit(4 INV2PAIR name($4) pin(0 4) pin(1 3) pin(2 4) - pin(4 7) - pin(5 8) + pin(3 10) + pin(4 9) + pin(5 11) pin(6 3) ) circuit(5 INV2PAIR name($5) pin(0 4) pin(1 3) pin(2 4) - pin(4 8) + pin(3 12) + pin(4 11) pin(5 5) pin(6 3) ) @@ -980,10 +1064,14 @@ xref( ) circuit(RINGO RINGO match xref( - net(5 6 match) - net(6 5 match) + net(8 6 match) net(7 8 match) - net(8 7 match) + net(6 10 match) + net(5 12 match) + net(9 7 match) + net(10 5 match) + net(11 11 match) + net(12 9 match) net(1 1 match) net(2 2 match) net(3 3 match) diff --git a/testdata/algo/lvs_test1_au.lvsdb.2 b/testdata/algo/lvs_test1_au.lvsdb.2 index cf52cf8cd..dac6d562b 100644 --- a/testdata/algo/lvs_test1_au.lvsdb.2 +++ b/testdata/algo/lvs_test1_au.lvsdb.2 @@ -655,7 +655,7 @@ layout( rect(metal2_lbl (-21301 -381) (2 2)) ) net(5 - rect(diff_cont (1730 90) (220 220)) + rect(diff_cont (14930 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -673,7 +673,7 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(6 - rect(diff_cont (17570 90) (220 220)) + rect(diff_cont (9650 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -691,7 +691,7 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(7 - rect(diff_cont (12290 90) (220 220)) + rect(diff_cont (4370 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -709,6 +709,78 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(8 + rect(diff_cont (-910 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(9 + rect(diff_cont (1730 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(10 + rect(diff_cont (17570 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(11 + rect(diff_cont (12290 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(12 rect(diff_cont (7010 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -739,7 +811,7 @@ layout( pin(1 3) pin(2 4) pin(3 1) - pin(4 6) + pin(4 10) pin(5 2) pin(6 3) ) @@ -747,32 +819,36 @@ layout( pin(0 4) pin(1 3) pin(2 4) + pin(3 8) pin(4 1) - pin(5 5) + pin(5 9) pin(6 3) ) circuit(3 INV2PAIR location(3580 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 5) - pin(5 8) + pin(3 7) + pin(4 9) + pin(5 12) pin(6 3) ) circuit(4 INV2PAIR location(8860 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 8) - pin(5 7) + pin(3 6) + pin(4 12) + pin(5 11) pin(6 3) ) circuit(5 INV2PAIR location(14140 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 7) - pin(5 6) + pin(3 5) + pin(4 11) + pin(5 10) pin(6 3) ) @@ -882,9 +958,13 @@ reference( net(3 name('3')) net(4 name('4')) net(5 name('6')) - net(6 name('5')) - net(7 name('8')) - net(8 name('7')) + net(6 name('100')) + net(7 name('5')) + net(8 name('101')) + net(9 name('8')) + net(10 name('102')) + net(11 name('7')) + net(12 name('103')) # Outgoing pins and their connections to nets pin(1 name('1')) @@ -906,31 +986,35 @@ reference( pin(0 4) pin(1 3) pin(2 4) + pin(3 6) pin(4 1) - pin(5 6) + pin(5 7) pin(6 3) ) circuit(3 INV2PAIR name($3) pin(0 4) pin(1 3) pin(2 4) - pin(4 6) - pin(5 7) + pin(3 8) + pin(4 7) + pin(5 9) pin(6 3) ) circuit(4 INV2PAIR name($4) pin(0 4) pin(1 3) pin(2 4) - pin(4 7) - pin(5 8) + pin(3 10) + pin(4 9) + pin(5 11) pin(6 3) ) circuit(5 INV2PAIR name($5) pin(0 4) pin(1 3) pin(2 4) - pin(4 8) + pin(3 12) + pin(4 11) pin(5 5) pin(6 3) ) @@ -980,10 +1064,14 @@ xref( ) circuit(RINGO RINGO match xref( - net(5 6 match) - net(6 5 match) + net(8 6 match) net(7 8 match) - net(8 7 match) + net(6 10 match) + net(5 12 match) + net(9 7 match) + net(10 5 match) + net(11 11 match) + net(12 9 match) net(1 1 match) net(2 2 match) net(3 3 match) diff --git a/testdata/algo/lvs_test1b_au.lvsdb.1 b/testdata/algo/lvs_test1b_au.lvsdb.1 index ca44150de..460cae8e7 100644 --- a/testdata/algo/lvs_test1b_au.lvsdb.1 +++ b/testdata/algo/lvs_test1b_au.lvsdb.1 @@ -655,7 +655,7 @@ layout( rect(metal2_lbl (-21301 -381) (2 2)) ) net(5 - rect(diff_cont (1730 90) (220 220)) + rect(diff_cont (14930 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -673,7 +673,7 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(6 - rect(diff_cont (17570 90) (220 220)) + rect(diff_cont (9650 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -691,7 +691,7 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(7 - rect(diff_cont (12290 90) (220 220)) + rect(diff_cont (4370 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -709,6 +709,78 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(8 + rect(diff_cont (-910 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(9 + rect(diff_cont (1730 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(10 + rect(diff_cont (17570 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(11 + rect(diff_cont (12290 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(12 rect(diff_cont (7010 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -739,7 +811,7 @@ layout( pin(1 3) pin(2 4) pin(3 1) - pin(4 6) + pin(4 10) pin(5 2) pin(6 3) ) @@ -747,32 +819,36 @@ layout( pin(0 4) pin(1 3) pin(2 4) + pin(3 8) pin(4 1) - pin(5 5) + pin(5 9) pin(6 3) ) circuit(3 INV2PAIR location(3580 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 5) - pin(5 8) + pin(3 7) + pin(4 9) + pin(5 12) pin(6 3) ) circuit(4 INV2PAIR location(8860 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 8) - pin(5 7) + pin(3 6) + pin(4 12) + pin(5 11) pin(6 3) ) circuit(5 INV2PAIR location(14140 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 7) - pin(5 6) + pin(3 5) + pin(4 11) + pin(5 10) pin(6 3) ) @@ -882,9 +958,13 @@ reference( net(3 name('3')) net(4 name('4')) net(5 name('6')) - net(6 name('5')) - net(7 name('8')) - net(8 name('7')) + net(6 name('100')) + net(7 name('5')) + net(8 name('101')) + net(9 name('8')) + net(10 name('102')) + net(11 name('7')) + net(12 name('103')) # Outgoing pins and their connections to nets pin(1 name('1')) @@ -906,31 +986,35 @@ reference( pin(0 4) pin(1 3) pin(2 4) + pin(3 6) pin(4 1) - pin(5 6) + pin(5 7) pin(6 3) ) circuit(3 INV2PAIR name($3) pin(0 4) pin(1 3) pin(2 4) - pin(4 6) - pin(5 7) + pin(3 8) + pin(4 7) + pin(5 9) pin(6 3) ) circuit(4 INV2PAIR name($4) pin(0 4) pin(1 3) pin(2 4) - pin(4 7) - pin(5 8) + pin(3 10) + pin(4 9) + pin(5 11) pin(6 3) ) circuit(5 INV2PAIR name($5) pin(0 4) pin(1 3) pin(2 4) - pin(4 8) + pin(3 12) + pin(4 11) pin(5 5) pin(6 3) ) @@ -980,10 +1064,14 @@ xref( ) circuit(RINGO RINGO match xref( - net(5 6 match) - net(6 5 match) + net(8 6 match) net(7 8 match) - net(8 7 match) + net(6 10 match) + net(5 12 match) + net(9 7 match) + net(10 5 match) + net(11 11 match) + net(12 9 match) net(1 1 match) net(2 2 match) net(3 3 match) diff --git a/testdata/algo/lvs_test1b_au.lvsdb.2 b/testdata/algo/lvs_test1b_au.lvsdb.2 index 2db900155..2853d93ef 100644 --- a/testdata/algo/lvs_test1b_au.lvsdb.2 +++ b/testdata/algo/lvs_test1b_au.lvsdb.2 @@ -655,7 +655,7 @@ layout( rect(metal2_lbl (-21301 -381) (2 2)) ) net(5 - rect(diff_cont (1730 90) (220 220)) + rect(diff_cont (14930 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -673,7 +673,7 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(6 - rect(diff_cont (17570 90) (220 220)) + rect(diff_cont (9650 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -691,7 +691,7 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(7 - rect(diff_cont (12290 90) (220 220)) + rect(diff_cont (4370 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -709,6 +709,78 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(8 + rect(diff_cont (-910 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(9 + rect(diff_cont (1730 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(10 + rect(diff_cont (17570 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(11 + rect(diff_cont (12290 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(12 rect(diff_cont (7010 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -739,7 +811,7 @@ layout( pin(1 3) pin(2 4) pin(3 1) - pin(4 6) + pin(4 10) pin(5 2) pin(6 3) ) @@ -747,32 +819,36 @@ layout( pin(0 4) pin(1 3) pin(2 4) + pin(3 8) pin(4 1) - pin(5 5) + pin(5 9) pin(6 3) ) circuit(3 INV2PAIR location(3580 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 5) - pin(5 8) + pin(3 7) + pin(4 9) + pin(5 12) pin(6 3) ) circuit(4 INV2PAIR location(8860 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 8) - pin(5 7) + pin(3 6) + pin(4 12) + pin(5 11) pin(6 3) ) circuit(5 INV2PAIR location(14140 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 7) - pin(5 6) + pin(3 5) + pin(4 11) + pin(5 10) pin(6 3) ) @@ -882,9 +958,13 @@ reference( net(3 name('3')) net(4 name('4')) net(5 name('6')) - net(6 name('5')) - net(7 name('8')) - net(8 name('7')) + net(6 name('100')) + net(7 name('5')) + net(8 name('101')) + net(9 name('8')) + net(10 name('102')) + net(11 name('7')) + net(12 name('103')) # Outgoing pins and their connections to nets pin(1 name('1')) @@ -906,31 +986,35 @@ reference( pin(0 4) pin(1 3) pin(2 4) + pin(3 6) pin(4 1) - pin(5 6) + pin(5 7) pin(6 3) ) circuit(3 INV2PAIR name($3) pin(0 4) pin(1 3) pin(2 4) - pin(4 6) - pin(5 7) + pin(3 8) + pin(4 7) + pin(5 9) pin(6 3) ) circuit(4 INV2PAIR name($4) pin(0 4) pin(1 3) pin(2 4) - pin(4 7) - pin(5 8) + pin(3 10) + pin(4 9) + pin(5 11) pin(6 3) ) circuit(5 INV2PAIR name($5) pin(0 4) pin(1 3) pin(2 4) - pin(4 8) + pin(3 12) + pin(4 11) pin(5 5) pin(6 3) ) @@ -980,10 +1064,14 @@ xref( ) circuit(RINGO RINGO match xref( - net(5 6 match) - net(6 5 match) + net(8 6 match) net(7 8 match) - net(8 7 match) + net(6 10 match) + net(5 12 match) + net(9 7 match) + net(10 5 match) + net(11 11 match) + net(12 9 match) net(1 1 match) net(2 2 match) net(3 3 match) diff --git a/testdata/algo/lvs_test2_au.lvsdb.1 b/testdata/algo/lvs_test2_au.lvsdb.1 index 85ec734bf..5526f557a 100644 --- a/testdata/algo/lvs_test2_au.lvsdb.1 +++ b/testdata/algo/lvs_test2_au.lvsdb.1 @@ -655,7 +655,7 @@ layout( rect(metal2_lbl (-21301 -381) (2 2)) ) net(5 - rect(diff_cont (1730 90) (220 220)) + rect(diff_cont (14930 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -673,7 +673,7 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(6 - rect(diff_cont (17570 90) (220 220)) + rect(diff_cont (9650 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -691,7 +691,7 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(7 - rect(diff_cont (12290 90) (220 220)) + rect(diff_cont (4370 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -709,6 +709,78 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(8 + rect(diff_cont (-910 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(9 + rect(diff_cont (1730 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(10 + rect(diff_cont (17570 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(11 + rect(diff_cont (12290 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(12 rect(diff_cont (7010 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -739,7 +811,7 @@ layout( pin(1 3) pin(2 4) pin(3 1) - pin(4 6) + pin(4 10) pin(5 2) pin(6 3) ) @@ -747,32 +819,36 @@ layout( pin(0 4) pin(1 3) pin(2 4) + pin(3 8) pin(4 1) - pin(5 5) + pin(5 9) pin(6 3) ) circuit(3 INV2PAIR location(3580 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 5) - pin(5 8) + pin(3 7) + pin(4 9) + pin(5 12) pin(6 3) ) circuit(4 INV2PAIR location(8860 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 8) - pin(5 7) + pin(3 6) + pin(4 12) + pin(5 11) pin(6 3) ) circuit(5 INV2PAIR location(14140 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 7) - pin(5 6) + pin(3 5) + pin(4 11) + pin(5 10) pin(6 3) ) @@ -874,8 +950,11 @@ reference( net(4 name('4')) net(5 name('6')) net(6 name('5')) - net(7 name('8')) - net(8 name('7')) + net(7 name('101')) + net(8 name('8')) + net(9 name('102')) + net(10 name('7')) + net(11 name('103')) # Outgoing pins and their connections to nets pin(1 name('1')) @@ -906,23 +985,26 @@ reference( pin(0 4) pin(1 3) pin(2 4) + pin(3 7) pin(4 6) - pin(5 7) + pin(5 8) pin(6 3) ) circuit(4 INV2PAIR name($4) pin(0 4) pin(1 3) pin(2 4) - pin(4 7) - pin(5 8) + pin(3 9) + pin(4 8) + pin(5 10) pin(6 3) ) circuit(5 INV2PAIR name($5) pin(0 4) pin(1 3) pin(2 4) - pin(4 8) + pin(3 11) + pin(4 10) pin(5 5) pin(6 3) ) diff --git a/testdata/algo/lvs_test2_au.lvsdb.2 b/testdata/algo/lvs_test2_au.lvsdb.2 index 9dacebd21..84e349abc 100644 --- a/testdata/algo/lvs_test2_au.lvsdb.2 +++ b/testdata/algo/lvs_test2_au.lvsdb.2 @@ -655,7 +655,7 @@ layout( rect(metal2_lbl (-21301 -381) (2 2)) ) net(5 - rect(diff_cont (1730 90) (220 220)) + rect(diff_cont (14930 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -673,7 +673,7 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(6 - rect(diff_cont (17570 90) (220 220)) + rect(diff_cont (9650 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -691,7 +691,7 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(7 - rect(diff_cont (12290 90) (220 220)) + rect(diff_cont (4370 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -709,6 +709,78 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(8 + rect(diff_cont (-910 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(9 + rect(diff_cont (1730 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(10 + rect(diff_cont (17570 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(11 + rect(diff_cont (12290 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(12 rect(diff_cont (7010 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -739,7 +811,7 @@ layout( pin(1 3) pin(2 4) pin(3 1) - pin(4 6) + pin(4 10) pin(5 2) pin(6 3) ) @@ -747,32 +819,36 @@ layout( pin(0 4) pin(1 3) pin(2 4) + pin(3 8) pin(4 1) - pin(5 5) + pin(5 9) pin(6 3) ) circuit(3 INV2PAIR location(3580 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 5) - pin(5 8) + pin(3 7) + pin(4 9) + pin(5 12) pin(6 3) ) circuit(4 INV2PAIR location(8860 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 8) - pin(5 7) + pin(3 6) + pin(4 12) + pin(5 11) pin(6 3) ) circuit(5 INV2PAIR location(14140 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 7) - pin(5 6) + pin(3 5) + pin(4 11) + pin(5 10) pin(6 3) ) @@ -874,8 +950,11 @@ reference( net(4 name('4')) net(5 name('6')) net(6 name('5')) - net(7 name('8')) - net(8 name('7')) + net(7 name('101')) + net(8 name('8')) + net(9 name('102')) + net(10 name('7')) + net(11 name('103')) # Outgoing pins and their connections to nets pin(1 name('1')) @@ -906,23 +985,26 @@ reference( pin(0 4) pin(1 3) pin(2 4) + pin(3 7) pin(4 6) - pin(5 7) + pin(5 8) pin(6 3) ) circuit(4 INV2PAIR name($4) pin(0 4) pin(1 3) pin(2 4) - pin(4 7) - pin(5 8) + pin(3 9) + pin(4 8) + pin(5 10) pin(6 3) ) circuit(5 INV2PAIR name($5) pin(0 4) pin(1 3) pin(2 4) - pin(4 8) + pin(3 11) + pin(4 10) pin(5 5) pin(6 3) ) diff --git a/testdata/algo/lvs_test2b_au.lvsdb.1 b/testdata/algo/lvs_test2b_au.lvsdb.1 index f0a00dfb1..612ed7a51 100644 --- a/testdata/algo/lvs_test2b_au.lvsdb.1 +++ b/testdata/algo/lvs_test2b_au.lvsdb.1 @@ -655,7 +655,7 @@ layout( rect(metal2_lbl (-21301 -381) (2 2)) ) net(5 - rect(diff_cont (1730 90) (220 220)) + rect(diff_cont (14930 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -673,7 +673,7 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(6 - rect(diff_cont (17570 90) (220 220)) + rect(diff_cont (9650 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -691,7 +691,7 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(7 - rect(diff_cont (12290 90) (220 220)) + rect(diff_cont (4370 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -709,6 +709,78 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(8 + rect(diff_cont (-910 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(9 + rect(diff_cont (1730 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(10 + rect(diff_cont (17570 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(11 + rect(diff_cont (12290 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(12 rect(diff_cont (7010 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -739,7 +811,7 @@ layout( pin(1 3) pin(2 4) pin(3 1) - pin(4 6) + pin(4 10) pin(5 2) pin(6 3) ) @@ -747,32 +819,36 @@ layout( pin(0 4) pin(1 3) pin(2 4) + pin(3 8) pin(4 1) - pin(5 5) + pin(5 9) pin(6 3) ) circuit(3 INV2PAIR location(3580 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 5) - pin(5 8) + pin(3 7) + pin(4 9) + pin(5 12) pin(6 3) ) circuit(4 INV2PAIR location(8860 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 8) - pin(5 7) + pin(3 6) + pin(4 12) + pin(5 11) pin(6 3) ) circuit(5 INV2PAIR location(14140 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 7) - pin(5 6) + pin(3 5) + pin(4 11) + pin(5 10) pin(6 3) ) @@ -874,8 +950,11 @@ reference( net(4 name('4')) net(5 name('6')) net(6 name('5')) - net(7 name('8')) - net(8 name('7')) + net(7 name('101')) + net(8 name('8')) + net(9 name('102')) + net(10 name('7')) + net(11 name('103')) # Outgoing pins and their connections to nets pin(1 name('1')) @@ -906,23 +985,26 @@ reference( pin(0 4) pin(1 3) pin(2 4) + pin(3 7) pin(4 6) - pin(5 7) + pin(5 8) pin(6 3) ) circuit(4 INV2PAIR name($4) pin(0 4) pin(1 3) pin(2 4) - pin(4 7) - pin(5 8) + pin(3 9) + pin(4 8) + pin(5 10) pin(6 3) ) circuit(5 INV2PAIR name($5) pin(0 4) pin(1 3) pin(2 4) - pin(4 8) + pin(3 11) + pin(4 10) pin(5 5) pin(6 3) ) diff --git a/testdata/algo/lvs_test2b_au.lvsdb.2 b/testdata/algo/lvs_test2b_au.lvsdb.2 index 1cf9af670..965381b39 100644 --- a/testdata/algo/lvs_test2b_au.lvsdb.2 +++ b/testdata/algo/lvs_test2b_au.lvsdb.2 @@ -655,7 +655,7 @@ layout( rect(metal2_lbl (-21301 -381) (2 2)) ) net(5 - rect(diff_cont (1730 90) (220 220)) + rect(diff_cont (14930 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -673,7 +673,7 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(6 - rect(diff_cont (17570 90) (220 220)) + rect(diff_cont (9650 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -691,7 +691,7 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(7 - rect(diff_cont (12290 90) (220 220)) + rect(diff_cont (4370 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -709,6 +709,78 @@ layout( rect(diff_cont (-220 180) (220 220)) ) net(8 + rect(diff_cont (-910 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(9 + rect(diff_cont (1730 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(10 + rect(diff_cont (17570 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(11 + rect(diff_cont (12290 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) + net(12 rect(diff_cont (7010 90) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -739,7 +811,7 @@ layout( pin(1 3) pin(2 4) pin(3 1) - pin(4 6) + pin(4 10) pin(5 2) pin(6 3) ) @@ -747,32 +819,36 @@ layout( pin(0 4) pin(1 3) pin(2 4) + pin(3 8) pin(4 1) - pin(5 5) + pin(5 9) pin(6 3) ) circuit(3 INV2PAIR location(3580 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 5) - pin(5 8) + pin(3 7) + pin(4 9) + pin(5 12) pin(6 3) ) circuit(4 INV2PAIR location(8860 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 8) - pin(5 7) + pin(3 6) + pin(4 12) + pin(5 11) pin(6 3) ) circuit(5 INV2PAIR location(14140 -800) pin(0 4) pin(1 3) pin(2 4) - pin(4 7) - pin(5 6) + pin(3 5) + pin(4 11) + pin(5 10) pin(6 3) ) @@ -874,8 +950,11 @@ reference( net(4 name('4')) net(5 name('6')) net(6 name('5')) - net(7 name('8')) - net(8 name('7')) + net(7 name('101')) + net(8 name('8')) + net(9 name('102')) + net(10 name('7')) + net(11 name('103')) # Outgoing pins and their connections to nets pin(1 name('1')) @@ -906,23 +985,26 @@ reference( pin(0 4) pin(1 3) pin(2 4) + pin(3 7) pin(4 6) - pin(5 7) + pin(5 8) pin(6 3) ) circuit(4 INV2PAIR name($4) pin(0 4) pin(1 3) pin(2 4) - pin(4 7) - pin(5 8) + pin(3 9) + pin(4 8) + pin(5 10) pin(6 3) ) circuit(5 INV2PAIR name($5) pin(0 4) pin(1 3) pin(2 4) - pin(4 8) + pin(3 11) + pin(4 10) pin(5 5) pin(6 3) ) diff --git a/testdata/algo/nreader10.cir b/testdata/algo/nreader10.cir new file mode 100644 index 000000000..f7e8a574e --- /dev/null +++ b/testdata/algo/nreader10.cir @@ -0,0 +1,10 @@ + +.global vdd gnd + +X0 FILLER_CAP +R$1 vdd gnd 1k + +.subckt FILLER_CAP +M0 gnd vdd gnd gnd NMOS W=10u L=10u +.ends FILLER_CAP + diff --git a/testdata/algo/nreader8.cir b/testdata/algo/nreader8.cir new file mode 100644 index 000000000..5a655897d --- /dev/null +++ b/testdata/algo/nreader8.cir @@ -0,0 +1,5 @@ + +.include "nreader8a.cir" +.include ../algo/nreader8b.cir +.inc nreader8c.cir + diff --git a/testdata/algo/nreader8a.cir b/testdata/algo/nreader8a.cir new file mode 100644 index 000000000..929d24588 --- /dev/null +++ b/testdata/algo/nreader8a.cir @@ -0,0 +1,4 @@ +.subckt INVX1 1 2 3 4 5 6 + .include nreader8x.cir +.ends + diff --git a/testdata/algo/nreader8b.cir b/testdata/algo/nreader8b.cir new file mode 100644 index 000000000..ddd4bee8c --- /dev/null +++ b/testdata/algo/nreader8b.cir @@ -0,0 +1,8 @@ + +.subckt ND2X1 1 2 3 4 5 6 7 + m$1 2 6 1 4 MLVPMOS L=0.25um W=1.5um + m$2 1 5 2 4 MLVPMOS L=0.25um W=1.5um + m$3 3 6 8 7 MLVNMOS L=0.25um W=0.95um + m$4 8 5 2 7 MLVNMOS L=0.25um W=0.95um +.ends ND2X1 + diff --git a/testdata/algo/nreader8c.cir b/testdata/algo/nreader8c.cir new file mode 100644 index 000000000..cb91dbfa5 --- /dev/null +++ b/testdata/algo/nreader8c.cir @@ -0,0 +1,15 @@ +.subckt RINGO 11 12 13 14 15 + x$1 12 1 15 12 11 14 15 ND2X1 + x$2 12 2 15 12 1 15 INVX1 + x$3 12 3 15 12 2 15 INVX1 + x$4 12 4 15 12 3 15 INVX1 + x$5 12 5 15 12 4 15 INVX1 + x$6 12 6 15 12 5 15 INVX1 + x$7 12 7 15 12 6 15 INVX1 + x$8 12 8 15 12 7 15 INVX1 + x$9 12 9 15 12 8 15 INVX1 + x$10 12 10 15 12 9 15 INVX1 + x$11 12 11 15 12 10 15 INVX1 + x$12 12 13 15 12 11 15 INVX1 +.ends RINGO + diff --git a/testdata/algo/nreader8x.cir b/testdata/algo/nreader8x.cir new file mode 100644 index 000000000..f3a8e9ced --- /dev/null +++ b/testdata/algo/nreader8x.cir @@ -0,0 +1,3 @@ +m$1 1 5 2 4 mlvpmos w=1.5um l=0.25um +m$2 3 5 2 6 mlvnmos w=0.95um l=0.25um + diff --git a/testdata/algo/nreader9.cir b/testdata/algo/nreader9.cir new file mode 100644 index 000000000..302b7a0a2 --- /dev/null +++ b/testdata/algo/nreader9.cir @@ -0,0 +1,12 @@ + +R$1 1 2 1.7k M=2 +R$2 3 4 1.7k +M$1 1 2 3 4 NMOS W=2u L=7u M=2 +M$2 1 2 3 4 PMOS W=2u L=7u +C$1 1 2 1e-9 M=2 +C$2 3 4 1e-9 +D$1 1 2 DIODE A=10P M=2 +D$2 3 4 DIODE A=10P +Q$1 1 2 3 4 BIP AE=10P M=2 +Q$2 1 2 3 4 BIP AE=10P + diff --git a/testdata/lvs/floating.cir b/testdata/lvs/floating.cir new file mode 100644 index 000000000..ced9a2759 --- /dev/null +++ b/testdata/lvs/floating.cir @@ -0,0 +1,50 @@ +* Extracted by KLayout + +* cell TOP +* pin A +* pin C +* pin SUBSTRATE +.SUBCKT TOP 2 3 4 +* net 2 A +* net 3 C +* net 4 SUBSTRATE +* cell instance $1 r0 *1 0,0 +X$1 2 3 1 6 4 DINV +* cell instance $2 r0 *1 3.6,0 +X$2 5 6 1 4 INVX1 +.ENDS TOP + +* cell DINV +* pin A<1> +* pin A<2> +* pin B<2> +* pin VDD +* pin VSS +.SUBCKT DINV 1 2 3 5 6 +* net 1 A<1> +* net 2 A<2> +* net 3 B<2> +* net 4 B<1> +* net 5 VDD +* net 6 VSS +* cell instance $1 r0 *1 0,0 +X$1 4 5 1 6 INVX1 +* cell instance $2 r0 *1 1.8,0 +X$2 3 5 2 6 INVX1 +.ENDS DINV + +* cell INVX1 +* pin OUT +* pin VDD +* pin IN +* pin VSS +.SUBCKT INVX1 1 2 3 4 +* net 1 OUT +* net 2 VDD +* net 3 IN +* net 4 VSS +* device instance $1 r0 *1 0.85,2.135 NMOS +M$1 4 3 1 4 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +* device instance $2 r0 *1 0.85,5.8 PMOS +M$2 2 3 1 2 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +.ENDS INVX1 diff --git a/testdata/lvs/floating.gds b/testdata/lvs/floating.gds new file mode 100644 index 000000000..3329c14d1 Binary files /dev/null and b/testdata/lvs/floating.gds differ diff --git a/testdata/lvs/floating.lvs b/testdata/lvs/floating.lvs new file mode 100644 index 000000000..2bdc842f1 --- /dev/null +++ b/testdata/lvs/floating.lvs @@ -0,0 +1,75 @@ + +source($lvs_test_source, $lvs_test_top) + +report_lvs($lvs_test_target_lvsdb, true) + +target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout") + +schematic("floating_ref.cir") + +deep + +# Drawing layers + +nwell = input(1, 0) +active = input(2, 0) +pplus = input(3, 0) +nplus = input(4, 0) +poly = input(5, 0) +contact = input(8, 0) +metal1 = input(9, 0) +via1 = input(10, 0) +metal2 = input(11, 0) + +# Bulk layer for terminal provisioning + +bulk = polygon_layer + +# Computed layers + +active_in_nwell = active & nwell +pactive = active_in_nwell & pplus +pgate = pactive & poly +psd = pactive - pgate +ntie = active_in_nwell & nplus + +active_outside_nwell = active - nwell +nactive = active_outside_nwell & nplus +ngate = nactive & poly +nsd = nactive - ngate +ptie = active_outside_nwell & pplus + +# Device extraction + +# PMOS transistor device extraction +extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell, + "tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell }) + +# NMOS transistor device extraction +extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk, + "tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk }) + +# Define connectivity for netlist extraction + +# Inter-layer +connect(psd, contact) +connect(nsd, contact) +connect(poly, contact) +connect(ntie, contact) +connect(nwell, ntie) +connect(ptie, contact) +connect(contact, metal1) +connect(metal1, via1) +connect(via1, metal2) + +# Global +connect_global(bulk, "SUBSTRATE") +connect_global(ptie, "SUBSTRATE") + +# Compare section + +netlist.simplify +align + +compare + diff --git a/testdata/lvs/floating.lvsdb b/testdata/lvs/floating.lvsdb new file mode 100644 index 000000000..3775e7da4 --- /dev/null +++ b/testdata/lvs/floating.lvsdb @@ -0,0 +1,454 @@ +#%lvsdb-klayout + +# Layout +layout( + top(TOP) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '5/0') + layer(l13 '5/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(2 name(VDD) + rect(l3 (-100 4500) (2000 3500)) + rect(l8 (-1090 -890) (180 180)) + rect(l8 (-580 -1030) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-590 1460) (1800 800)) + rect(l11 (-1050 -550) (300 300)) + rect(l11 (-700 -850) (300 300)) + rect(l11 (299 499) (2 2)) + rect(l11 (-601 -2201) (300 1400)) + rect(l2 (-350 -1450) (425 1500)) + rect(l9 (-75 450) (500 500)) + ) + net(3 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 -1840) (250 1450)) + rect(l4 (-250 1940) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l8 (-465 -3790) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(4 name(VSS) + rect(l8 (810 710) (180 180)) + rect(l8 (-580 880) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-590 -2100) (1800 800)) + rect(l11 (-1050 -550) (300 300)) + rect(l11 (-101 -151) (2 2)) + rect(l11 (-601 399) (300 1360)) + rect(l6 (-350 -900) (425 950)) + rect(l10 (-75 -2010) (500 400)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(OUT)) + pin(2 name(VDD)) + pin(3 name(IN)) + pin(4 name(VSS)) + + # Devices and their connections + device(1 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 4) + terminal(G 3) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 2) + terminal(G 3) + terminal(D 1) + terminal(B 2) + ) + + ) + circuit(DINV + + # Circuit boundary + rect((-100 400) (3800 7600)) + + # Nets with their geometries + net(1 name('A<1>') + rect(l8 (510 3010) (180 180)) + rect(l11 (-91 -91) (2 2)) + ) + net(2 name('A<2>') + rect(l8 (2310 3010) (180 180)) + rect(l11 (-91 -91) (2 2)) + ) + net(3 name('B<2>') + rect(l11 (2999 3999) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(4 name('B<1>') + rect(l11 (1199 3999) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(5 name(VDD) + rect(l11 (1799 7199) (2 2)) + rect(l2 (299 -2151) (425 1500)) + rect(l2 (-2225 -1500) (425 1500)) + ) + net(6 name(VSS) + rect(l11 (1799 799) (2 2)) + rect(l6 (299 859) (425 950)) + rect(l6 (-2225 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name('A<1>')) + pin(2 name('A<2>')) + pin(3 name('B<2>')) + pin(5 name(VDD)) + pin(6 name(VSS)) + + # Subcircuits and their connections + circuit(1 INVX1 location(0 0) + pin(0 4) + pin(1 5) + pin(2 1) + pin(3 6) + ) + circuit(2 INVX1 location(1800 0) + pin(0 3) + pin(1 5) + pin(2 2) + pin(3 6) + ) + + ) + circuit(TOP + + # Circuit boundary + rect((-100 400) (5600 7600)) + + # Nets with their geometries + net(1 + rect(l8 (4110 3010) (180 180)) + rect(l11 (-1190 -240) (950 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(2 name(A) + rect(l8 (510 3010) (180 180)) + rect(l11 (-91 -91) (2 2)) + ) + net(3 name(C) + rect(l8 (2310 3010) (180 180)) + rect(l11 (-91 -91) (2 2)) + ) + net(4 name(SUBSTRATE) + rect(l6 (3900 1660) (425 950)) + rect(l6 (-2225 -950) (425 950)) + rect(l6 (-2225 -950) (425 950)) + ) + net(5 + rect(l2 (4575 5050) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(6 + rect(l2 (3900 5050) (425 1500)) + rect(l2 (-2225 -1500) (425 1500)) + rect(l2 (-2225 -1500) (425 1500)) + ) + + # Outgoing pins and their connections to nets + pin(2 name(A)) + pin(3 name(C)) + pin(4 name(SUBSTRATE)) + + # Subcircuits and their connections + circuit(1 DINV location(0 0) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 6) + pin(4 4) + ) + circuit(2 INVX1 location(3600 0) + pin(0 5) + pin(1 6) + pin(2 1) + pin(3 4) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(NMOS MOS4) + class(PMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(INVX1 + + # Nets + net(1 name(A)) + net(2 name(Z)) + net(3 name(VDD)) + net(4 name(VSS)) + + # Outgoing pins and their connections to nets + pin(1 name(A)) + pin(2 name(Z)) + pin(3 name(VDD)) + pin(4 name(VSS)) + + # Devices and their connections + device(1 NMOS + name('0') + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 1) + terminal(D 4) + terminal(B 4) + ) + device(2 PMOS + name('1') + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 1) + terminal(D 3) + terminal(B 3) + ) + + ) + circuit(DINV + + # Nets + net(1 name('A<1>')) + net(2 name('A<2>')) + net(3 name('B<1>')) + net(4 name('B<2>')) + net(5 name(VDD)) + net(6 name(VSS)) + + # Outgoing pins and their connections to nets + pin(1 name('A<1>')) + pin(2 name('A<2>')) + pin(3 name('B<1>')) + pin(4 name('B<2>')) + pin(5 name(VDD)) + pin(6 name(VSS)) + + # Subcircuits and their connections + circuit(1 INVX1 name(A) + pin(0 1) + pin(1 3) + pin(2 5) + pin(3 6) + ) + circuit(2 INVX1 name(B) + pin(0 2) + pin(1 4) + pin(2 5) + pin(3 6) + ) + + ) + circuit(TOP + + # Nets + net(1 name(A)) + net(2 name(C)) + net(3 name(D)) + net(4 name(VDD)) + net(5 name(VSS)) + net(6 name(B)) + net(7 name(E)) + + # Outgoing pins and their connections to nets + pin(1 name(A)) + pin(2 name(C)) + pin(3 name(D)) + pin(4 name(VDD)) + pin(5 name(VSS)) + + # Subcircuits and their connections + circuit(1 DINV name('0') + pin(0 1) + pin(1 2) + pin(2 6) + pin(3 7) + pin(4 4) + pin(5 5) + ) + circuit(2 INVX1 name('1') + pin(0 7) + pin(1 3) + pin(2 4) + pin(3 5) + ) + + ) +) + +# Cross reference +xref( + circuit(DINV DINV match + xref( + net(1 1 match) + net(2 2 match) + net(4 3 warning) + net(3 4 warning) + net(5 5 match) + net(6 6 match) + pin(() 2 match) + pin(0 0 match) + pin(1 1 match) + pin(2 3 match) + pin(3 4 match) + pin(4 5 match) + circuit(1 1 match) + circuit(2 2 match) + ) + ) + circuit(INVX1 INVX1 match + xref( + net(3 1 match) + net(1 2 match) + net(2 3 match) + net(4 4 match) + pin(2 0 match) + pin(0 1 match) + pin(1 2 match) + pin(3 3 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(TOP TOP match + xref( + net(5 3 match) + net(1 7 match) + net(6 4 match) + net(2 1 match) + net(3 2 match) + net(4 5 match) + pin(() 2 match) + pin(() 3 match) + pin(0 0 match) + pin(1 1 match) + pin(2 4 match) + circuit(1 1 match) + circuit(2 2 match) + ) + ) +) diff --git a/testdata/lvs/floating_ref.cir b/testdata/lvs/floating_ref.cir new file mode 100644 index 000000000..a0f4dc332 --- /dev/null +++ b/testdata/lvs/floating_ref.cir @@ -0,0 +1,16 @@ +.global VDD VSS + +.subckt TOP A C D +X0 A C B E DINV +X1 E D INVX1 +.ends + +.subckt DINV A<1> A<2> B<1> B<2> +XA A<1> B<1> INVX1 +XB A<2> B<2> INVX1 +.ends + +.subckt INVX1 A Z +M0 Z A VSS VSS NMOS W=0.95U L=0.25U +M1 Z A VDD VDD PMOS W=1.5U L=0.25U +.ends diff --git a/testdata/lvs/ringo.gds b/testdata/lvs/ringo.gds index fa116f14d..c6a7aac64 100644 Binary files a/testdata/lvs/ringo.gds and b/testdata/lvs/ringo.gds differ diff --git a/testdata/lvs/ringo_device_subcircuits.cir b/testdata/lvs/ringo_device_subcircuits.cir new file mode 100644 index 000000000..761afb771 --- /dev/null +++ b/testdata/lvs/ringo_device_subcircuits.cir @@ -0,0 +1,83 @@ +* Extracted by KLayout + +* cell RINGO +* pin FB +* pin VDD +* pin OUT +* pin ENABLE +* pin VSS +.SUBCKT RINGO 11 12 13 14 15 +* net 11 FB +* net 12 VDD +* net 13 OUT +* net 14 ENABLE +* net 15 VSS +* cell instance $1 r0 *1 1.8,0 +X$1 12 1 15 12 11 14 15 ND2X1 +* cell instance $2 r0 *1 4.2,0 +X$2 12 2 15 12 1 15 INVX1 +* cell instance $3 r0 *1 6,0 +X$3 12 3 15 12 2 15 INVX1 +* cell instance $4 r0 *1 7.8,0 +X$4 12 4 15 12 3 15 INVX1 +* cell instance $5 r0 *1 9.6,0 +X$5 12 5 15 12 4 15 INVX1 +* cell instance $6 r0 *1 11.4,0 +X$6 12 6 15 12 5 15 INVX1 +* cell instance $7 r0 *1 13.2,0 +X$7 12 7 15 12 6 15 INVX1 +* cell instance $8 r0 *1 15,0 +X$8 12 8 15 12 7 15 INVX1 +* cell instance $9 r0 *1 16.8,0 +X$9 12 9 15 12 8 15 INVX1 +* cell instance $10 r0 *1 18.6,0 +X$10 12 10 15 12 9 15 INVX1 +* cell instance $11 r0 *1 20.4,0 +X$11 12 11 15 12 10 15 INVX1 +* cell instance $12 r0 *1 22.2,0 +X$12 12 13 15 12 11 15 INVX1 +.ENDS RINGO + +* cell INVX1 +* pin VDD +* pin OUT +* pin VSS +* pin +* pin IN +* pin SUBSTRATE +.SUBCKT INVX1 1 2 3 4 5 6 +* net 1 VDD +* net 2 OUT +* net 3 VSS +* net 5 IN +* net 6 SUBSTRATE +* device instance $1 r0 *1 0.85,5.8 PMOS +M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +* device instance $2 r0 *1 0.85,2.135 NMOS +M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +.ENDS INVX1 + +* cell ND2X1 +* pin VDD +* pin OUT +* pin VSS +* pin +* pin B +* pin A +* pin SUBSTRATE +.SUBCKT ND2X1 1 2 3 4 5 6 7 +* net 1 VDD +* net 2 OUT +* net 3 VSS +* net 5 B +* net 6 A +* net 7 SUBSTRATE +* device instance $1 r0 *1 0.85,5.8 PMOS +M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +* device instance $2 r0 *1 1.55,5.8 PMOS +M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +* device instance $3 r0 *1 0.85,2.135 NMOS +M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +* device instance $4 r0 *1 1.55,2.135 NMOS +M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +.ENDS ND2X1 diff --git a/testdata/lvs/ringo_device_subcircuits.lvs b/testdata/lvs/ringo_device_subcircuits.lvs new file mode 100644 index 000000000..83b63cec8 --- /dev/null +++ b/testdata/lvs/ringo_device_subcircuits.lvs @@ -0,0 +1,126 @@ + +source($lvs_test_source, "RINGO") + +report_lvs($lvs_test_target_lvsdb, true) + +target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout") + + +# Provide a special reader +class SubcircuitModelsReader < RBA::NetlistSpiceReaderDelegate + + # says we want to catch these subcircuits as devices + def wants_subcircuit(name) + name == "NMOS" || name == "XPMOS" + end + + # translate the element + def element(circuit, el, name, model, value, nets, params) + + if el != "X" + # all other elements are left to the standard implementation + return super + end + + if nets.size != 4 + error("Subcircuit #{model} needs four nodes") + end + + # provide a device class + cls = circuit.netlist.device_class_by_name(model) + if ! cls + cls = RBA::DeviceClassMOS4Transistor::new + cls.name = model + circuit.netlist.add(cls) + end + + # create a device + device = circuit.create_device(cls, name) + + # and configure the device + [ "S", "G", "D", "B" ].each_with_index do |t,index| + device.connect_terminal(t, nets[index]) + end + + # parameters in the model are given in micrometer units, so + # we need to translate the parameter values from SI to um values: + device.set_parameter("W", (params["W"] || 0.0) * 1e6) + device.set_parameter("L", (params["L"] || 0.0) * 1e6) + + return true + + end + +end + + +schematic("ringo_xdevice.cir", RBA::NetlistSpiceReader::new(SubcircuitModelsReader::new)) + +deep + +# Drawing layers + +nwell = input(1, 0) +active = input(2, 0) +pplus = input(3, 0) +nplus = input(4, 0) +poly = input(5, 0) +contact = input(8, 0) +metal1 = input(9, 0) +via1 = input(10, 0) +metal2 = input(11, 0) + +# Bulk layer for terminal provisioning + +bulk = polygon_layer + +# Computed layers + +active_in_nwell = active & nwell +pactive = active_in_nwell & pplus +pgate = pactive & poly +psd = pactive - pgate +ntie = active_in_nwell & nplus + +active_outside_nwell = active - nwell +nactive = active_outside_nwell & nplus +ngate = nactive & poly +nsd = nactive - ngate +ptie = active_outside_nwell & pplus + +# Device extraction + +# PMOS transistor device extraction +extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell, + "tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell }) + +# NMOS transistor device extraction +extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk, + "tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk }) + +# Define connectivity for netlist extraction + +# Inter-layer +connect(psd, contact) +connect(nsd, contact) +connect(poly, contact) +connect(ntie, contact) +connect(nwell, ntie) +connect(ptie, contact) +connect(contact, metal1) +connect(metal1, via1) +connect(via1, metal2) + +# Global +connect_global(bulk, "SUBSTRATE") +connect_global(ptie, "SUBSTRATE") + +# Test same_device_classes +same_device_classes("PMOS", "XPMOS") + +# Compare section + +netlist.simplify + +compare + diff --git a/testdata/lvs/ringo_device_subcircuits.lvsdb.1 b/testdata/lvs/ringo_device_subcircuits.lvsdb.1 new file mode 100644 index 000000000..46d09231c --- /dev/null +++ b/testdata/lvs/ringo_device_subcircuits.lvsdb.1 @@ -0,0 +1,971 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-1750 -1450) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l8 (4710 3010) (180 180)) + rect(l11 (-850 -240) (610 300)) + rect(l2 (-2550 1800) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(2 + rect(l8 (6510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 + rect(l8 (8310 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(4 + rect(l8 (10110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(5 + rect(l8 (11910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(6 + rect(l8 (13710 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(7 + rect(l8 (15510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(8 + rect(l8 (17310 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(9 + rect(l8 (19110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(10 + rect(l8 (20910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(11 name(FB) + rect(l8 (22710 3010) (180 180)) + rect(l8 (-19700 720) (180 180)) + rect(l11 (18380 -1140) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(12 name(VDD) + rect(l3 (500 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l8 (-24690 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-21741 859) (2 2)) + rect(l11 (-2351 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l2 (-23025 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l9 (-21975 -450) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(13 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + rect(l2 (-625 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(14 name(ENABLE) + rect(l8 (2510 3010) (180 180)) + rect(l11 (-250 -250) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(15 name(VSS) + rect(l8 (1110 1610) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-21741 -391) (2 2)) + rect(l11 (-1901 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l6 (-23700 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l10 (-21975 -2210) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(11 name(FB)) + pin(12 name(VDD)) + pin(13 name(OUT)) + pin(14 name(ENABLE)) + pin(15 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 12) + pin(1 1) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 14) + pin(6 15) + ) + circuit(2 INVX1 location(4200 0) + pin(0 12) + pin(1 2) + pin(2 15) + pin(3 12) + pin(4 1) + pin(5 15) + ) + circuit(3 INVX1 location(6000 0) + pin(0 12) + pin(1 3) + pin(2 15) + pin(3 12) + pin(4 2) + pin(5 15) + ) + circuit(4 INVX1 location(7800 0) + pin(0 12) + pin(1 4) + pin(2 15) + pin(3 12) + pin(4 3) + pin(5 15) + ) + circuit(5 INVX1 location(9600 0) + pin(0 12) + pin(1 5) + pin(2 15) + pin(3 12) + pin(4 4) + pin(5 15) + ) + circuit(6 INVX1 location(11400 0) + pin(0 12) + pin(1 6) + pin(2 15) + pin(3 12) + pin(4 5) + pin(5 15) + ) + circuit(7 INVX1 location(13200 0) + pin(0 12) + pin(1 7) + pin(2 15) + pin(3 12) + pin(4 6) + pin(5 15) + ) + circuit(8 INVX1 location(15000 0) + pin(0 12) + pin(1 8) + pin(2 15) + pin(3 12) + pin(4 7) + pin(5 15) + ) + circuit(9 INVX1 location(16800 0) + pin(0 12) + pin(1 9) + pin(2 15) + pin(3 12) + pin(4 8) + pin(5 15) + ) + circuit(10 INVX1 location(18600 0) + pin(0 12) + pin(1 10) + pin(2 15) + pin(3 12) + pin(4 9) + pin(5 15) + ) + circuit(11 INVX1 location(20400 0) + pin(0 12) + pin(1 11) + pin(2 15) + pin(3 12) + pin(4 10) + pin(5 15) + ) + circuit(12 INVX1 location(22200 0) + pin(0 12) + pin(1 13) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 15) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(XPMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 XPMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 XPMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 XPMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(10 15 match) + net(2 7 match) + net(3 8 match) + net(4 9 match) + net(5 10 match) + net(6 11 match) + net(7 12 match) + net(8 13 match) + net(9 14 match) + net(14 4 match) + net(11 3 match) + net(13 5 match) + net(12 2 match) + net(15 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(4 4 match) + circuit(5 5 match) + circuit(6 6 match) + circuit(7 7 match) + circuit(8 8 match) + circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_device_subcircuits.lvsdb.2 b/testdata/lvs/ringo_device_subcircuits.lvsdb.2 new file mode 100644 index 000000000..5f01d5105 --- /dev/null +++ b/testdata/lvs/ringo_device_subcircuits.lvsdb.2 @@ -0,0 +1,971 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l8 (4710 3010) (180 180)) + rect(l11 (-850 -240) (610 300)) + rect(l2 (-1175 1800) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) + ) + net(2 + rect(l8 (6510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 + rect(l8 (8310 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(4 + rect(l8 (10110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(5 + rect(l8 (11910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(6 + rect(l8 (13710 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(7 + rect(l8 (15510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(8 + rect(l8 (17310 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(9 + rect(l8 (19110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(10 + rect(l8 (20910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(11 name(FB) + rect(l8 (22710 3010) (180 180)) + rect(l8 (-19700 720) (180 180)) + rect(l11 (18380 -1140) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(12 name(VDD) + rect(l3 (500 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l8 (-24690 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-21741 859) (2 2)) + rect(l11 (-2351 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l2 (-23025 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l9 (-21975 -450) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(13 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + rect(l2 (-625 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(14 name(ENABLE) + rect(l8 (2510 3010) (180 180)) + rect(l11 (-250 -250) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(15 name(VSS) + rect(l8 (1110 1610) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-21741 -391) (2 2)) + rect(l11 (-1901 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l6 (-23700 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l10 (-21975 -2210) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(11 name(FB)) + pin(12 name(VDD)) + pin(13 name(OUT)) + pin(14 name(ENABLE)) + pin(15 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 12) + pin(1 1) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 14) + pin(6 15) + ) + circuit(2 INVX1 location(4200 0) + pin(0 12) + pin(1 2) + pin(2 15) + pin(3 12) + pin(4 1) + pin(5 15) + ) + circuit(3 INVX1 location(6000 0) + pin(0 12) + pin(1 3) + pin(2 15) + pin(3 12) + pin(4 2) + pin(5 15) + ) + circuit(4 INVX1 location(7800 0) + pin(0 12) + pin(1 4) + pin(2 15) + pin(3 12) + pin(4 3) + pin(5 15) + ) + circuit(5 INVX1 location(9600 0) + pin(0 12) + pin(1 5) + pin(2 15) + pin(3 12) + pin(4 4) + pin(5 15) + ) + circuit(6 INVX1 location(11400 0) + pin(0 12) + pin(1 6) + pin(2 15) + pin(3 12) + pin(4 5) + pin(5 15) + ) + circuit(7 INVX1 location(13200 0) + pin(0 12) + pin(1 7) + pin(2 15) + pin(3 12) + pin(4 6) + pin(5 15) + ) + circuit(8 INVX1 location(15000 0) + pin(0 12) + pin(1 8) + pin(2 15) + pin(3 12) + pin(4 7) + pin(5 15) + ) + circuit(9 INVX1 location(16800 0) + pin(0 12) + pin(1 9) + pin(2 15) + pin(3 12) + pin(4 8) + pin(5 15) + ) + circuit(10 INVX1 location(18600 0) + pin(0 12) + pin(1 10) + pin(2 15) + pin(3 12) + pin(4 9) + pin(5 15) + ) + circuit(11 INVX1 location(20400 0) + pin(0 12) + pin(1 11) + pin(2 15) + pin(3 12) + pin(4 10) + pin(5 15) + ) + circuit(12 INVX1 location(22200 0) + pin(0 12) + pin(1 13) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 15) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(XPMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 XPMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 XPMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 XPMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(10 15 match) + net(2 7 match) + net(3 8 match) + net(4 9 match) + net(5 10 match) + net(6 11 match) + net(7 12 match) + net(8 13 match) + net(9 14 match) + net(14 4 match) + net(11 3 match) + net(13 5 match) + net(12 2 match) + net(15 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(4 4 match) + circuit(5 5 match) + circuit(6 6 match) + circuit(7 7 match) + circuit(8 8 match) + circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_dummy_device.cir b/testdata/lvs/ringo_dummy_device.cir new file mode 100644 index 000000000..276b8d847 --- /dev/null +++ b/testdata/lvs/ringo_dummy_device.cir @@ -0,0 +1,28 @@ + +.SUBCKT RINGO VSS VDD FB ENABLE OUT +X$1 VDD 1 VSS VDD FB ENABLE VSS ND2X1 +X$2 VDD 2 VSS VDD 1 VSS INVX1 +X$3 VDD 3 VSS VDD 2 VSS INVX1 +X$4 VDD 4 VSS VDD 3 VSS INVX1 +X$5 VDD 5 VSS VDD 4 VSS INVX1 +X$6 VDD 6 VSS VDD 5 VSS INVX1 +X$7 VDD 7 VSS VDD 6 VSS INVX1 +X$8 VDD 8 VSS VDD 7 VSS INVX1 +X$9 VDD 9 VSS VDD 8 VSS INVX1 +X$10 VDD 10 VSS VDD 9 VSS INVX1 +X$11 VDD FB VSS VDD 10 VSS INVX1 +X$12 VDD OUT VSS VDD FB VSS INVX1 +M$1 VSS DUMMY VSS VSS NMOS L=0.25U W=0.95U +.ENDS RINGO + +.SUBCKT ND2X1 VDD OUT VSS NWELL B A BULK +M$1 OUT A VDD NWELL PMOS L=0.25U W=1.5U +M$2 VDD B OUT NWELL PMOS L=0.25U W=1.5U +M$3 VSS A 1 BULK NMOS L=0.25U W=0.95U +M$4 1 B OUT BULK NMOS L=0.25U W=0.95U +.ENDS ND2X1 + +.SUBCKT INVX1 VDD OUT VSS NWELL IN BULK +M$1 VDD IN OUT NWELL PMOS L=0.25U W=1.5U +M$2 VSS IN OUT BULK NMOS L=0.25U W=0.95U +.ENDS INVX1 diff --git a/testdata/lvs/ringo_dummy_device.gds b/testdata/lvs/ringo_dummy_device.gds new file mode 100644 index 000000000..5ff716ea4 Binary files /dev/null and b/testdata/lvs/ringo_dummy_device.gds differ diff --git a/testdata/lvs/ringo_mixed_hierarchy.cir b/testdata/lvs/ringo_mixed_hierarchy.cir new file mode 100644 index 000000000..8e98d778a --- /dev/null +++ b/testdata/lvs/ringo_mixed_hierarchy.cir @@ -0,0 +1,64 @@ +* Extracted by KLayout + +* cell RINGO +* pin B,FB +* pin A,ENABLE +* pin VDD +* pin OUT +* pin VSS +.SUBCKT RINGO 1 2 3 14 16 +* net 1 B,FB +* net 2 A,ENABLE +* net 3 VDD +* net 14 OUT +* net 16 VSS +* cell instance $1 r0 *1 22.2,0 +X$1 3 14 16 3 1 16 INVX1 +* cell instance $2 r0 *1 20.4,0 +X$2 3 1 16 3 13 16 INVX1 +* cell instance $8 r0 *1 4.2,0 +X$8 3 5 16 3 4 16 INVX1 +* cell instance $9 r0 *1 6,0 +X$9 3 6 16 3 5 16 INVX1 +* cell instance $10 r0 *1 7.8,0 +X$10 3 7 16 3 6 16 INVX1 +* cell instance $11 r0 *1 9.6,0 +X$11 3 8 16 3 7 16 INVX1 +* cell instance $12 r0 *1 11.4,0 +X$12 3 9 16 3 8 16 INVX1 +* cell instance $13 r0 *1 13.2,0 +X$13 3 10 16 3 9 16 INVX1 +* cell instance $14 r0 *1 15,0 +X$14 3 11 16 3 10 16 INVX1 +* cell instance $15 r0 *1 16.8,0 +X$15 3 12 16 3 11 16 INVX1 +* cell instance $16 r0 *1 18.6,0 +X$16 3 13 16 3 12 16 INVX1 +* device instance $1 r0 *1 2.65,5.8 PMOS +M$1 4 2 3 3 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +* device instance $2 r0 *1 3.35,5.8 PMOS +M$2 3 1 4 3 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +* device instance $3 r0 *1 2.65,2.135 NMOS +M$3 16 2 15 16 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +* device instance $4 r0 *1 3.35,2.135 NMOS +M$4 15 1 4 16 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +.ENDS RINGO + +* cell INVX1 +* pin VDD +* pin OUT +* pin VSS +* pin +* pin IN +* pin SUBSTRATE +.SUBCKT INVX1 1 2 3 4 5 6 +* net 1 VDD +* net 2 OUT +* net 3 VSS +* net 5 IN +* net 6 SUBSTRATE +* device instance $1 r0 *1 0.85,2.135 NMOS +M$1 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +* device instance $2 r0 *1 0.85,5.8 PMOS +M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +.ENDS INVX1 diff --git a/testdata/lvs/ringo_mixed_hierarchy.gds b/testdata/lvs/ringo_mixed_hierarchy.gds new file mode 100644 index 000000000..e498a3028 Binary files /dev/null and b/testdata/lvs/ringo_mixed_hierarchy.gds differ diff --git a/testdata/lvs/ringo_mixed_hierarchy.lvs b/testdata/lvs/ringo_mixed_hierarchy.lvs new file mode 100644 index 000000000..cba9caa86 --- /dev/null +++ b/testdata/lvs/ringo_mixed_hierarchy.lvs @@ -0,0 +1,76 @@ + +source($lvs_test_source, "RINGO") + +report_lvs($lvs_test_target_lvsdb, true) + +target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout") + +schematic("ringo.cir") + +deep + +# Drawing layers + +nwell = input(1, 0) +active = input(2, 0) +pplus = input(3, 0) +nplus = input(4, 0) +poly = input(5, 0) +contact = input(8, 0) +metal1 = input(9, 0) +via1 = input(10, 0) +metal2 = input(11, 0) + +# Bulk layer for terminal provisioning + +bulk = polygon_layer + +# Computed layers + +active_in_nwell = active & nwell +pactive = active_in_nwell & pplus +pgate = pactive & poly +psd = pactive - pgate +ntie = active_in_nwell & nplus + +active_outside_nwell = active - nwell +nactive = active_outside_nwell & nplus +ngate = nactive & poly +nsd = nactive - ngate +ptie = active_outside_nwell & pplus + +# Device extraction + +# PMOS transistor device extraction +extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell, + "tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell }) + +# NMOS transistor device extraction +extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk, + "tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk }) + +# Define connectivity for netlist extraction + +# Inter-layer +connect(psd, contact) +connect(nsd, contact) +connect(poly, contact) +connect(ntie, contact) +connect(nwell, ntie) +connect(ptie, contact) +connect(contact, metal1) +connect(metal1, via1) +connect(via1, metal2) + +# Global +connect_global(bulk, "SUBSTRATE") +connect_global(ptie, "SUBSTRATE") + +# Compare section + +netlist.simplify + +align + +compare + diff --git a/testdata/lvs/ringo_mixed_hierarchy.lvsdb b/testdata/lvs/ringo_mixed_hierarchy.lvsdb new file mode 100644 index 000000000..796a8d02b --- /dev/null +++ b/testdata/lvs/ringo_mixed_hierarchy.lvsdb @@ -0,0 +1,872 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 -1840) (250 1450)) + rect(l4 (-250 1940) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l8 (-465 -3790) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + device(2 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (25800 7650)) + + # Nets with their geometries + net(1 name('B,FB') + rect(l4 (3225 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l8 (19340 -1080) (180 180)) + rect(l11 (-19760 660) (300 300)) + rect(l11 (-131 -151) (2 2)) + rect(l11 (18449 -1051) (900 300)) + rect(l11 (-1390 590) (320 320)) + rect(l11 (-18460 -320) (320 320)) + rect(l12 (17880 -260) (200 200)) + rect(l12 (-18340 -200) (200 200)) + rect(l13 (100 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (17919 -201) (400 400)) + rect(l13 (-18540 -400) (400 400)) + rect(l2 (17895 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(2 name('A,ENABLE') + rect(l4 (2525 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 -1840) (250 1450)) + rect(l4 (-250 1940) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l8 (-265 -3790) (180 180)) + rect(l11 (-240 -240) (300 300)) + rect(l11 (-151 -151) (2 2)) + rect(l11 (-161 -161) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(3 name(VDD) + rect(l3 (1700 4500) (2600 3500)) + rect(l3 (-3800 -3500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l8 (-22890 -2840) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-1980 870) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-21840 -1290) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l11 (-102 48) (2 2)) + rect(l11 (-2351 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l2 (-23025 -2550) (450 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (3175 -1500) (425 1500)) + rect(l2 (-2225 -1500) (425 1500)) + rect(l9 (-20175 -450) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(4 + rect(l8 (3610 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (920 -2880) (180 180)) + polygon(l11 (-1340 -1480) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + rect(l11 (0 -1550) (610 300)) + polygon(l11 (-2500 1250) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-1890 600) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-1750 -1450) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(5 + rect(l8 (6510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(6 + rect(l8 (8310 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(7 + rect(l8 (10110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(8 + rect(l8 (11910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(9 + rect(l8 (13710 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(10 + rect(l8 (15510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(11 + rect(l8 (17310 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(12 + rect(l8 (19110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(13 + rect(l8 (20910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(14 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + rect(l2 (-625 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(15 + rect(l6 (2775 1660) (450 950)) + ) + net(16 name(VSS) + rect(l8 (2210 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1280 -890) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-22540 -40) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l11 (-102 48) (2 2)) + rect(l11 (-1901 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l6 (-23700 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (3175 -950) (425 950)) + rect(l6 (-2225 -950) (425 950)) + rect(l10 (-20175 -2210) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(1 name('B,FB')) + pin(2 name('A,ENABLE')) + pin(3 name(VDD)) + pin(14 name(OUT)) + pin(16 name(VSS)) + + # Devices and their connections + device(1 D$PMOS + location(2650 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 4) + terminal(G 2) + terminal(D 3) + terminal(B 3) + ) + device(2 D$PMOS$1 + location(3350 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 3) + terminal(G 1) + terminal(D 4) + terminal(B 3) + ) + device(3 D$NMOS + location(2650 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 16) + terminal(G 2) + terminal(D 15) + terminal(B 16) + ) + device(4 D$NMOS$1 + location(3350 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 15) + terminal(G 1) + terminal(D 4) + terminal(B 16) + ) + + # Subcircuits and their connections + circuit(1 INVX1 location(22200 0) + pin(0 3) + pin(1 14) + pin(2 16) + pin(3 3) + pin(4 1) + pin(5 16) + ) + circuit(2 INVX1 location(20400 0) + pin(0 3) + pin(1 1) + pin(2 16) + pin(3 3) + pin(4 13) + pin(5 16) + ) + circuit(8 INVX1 location(4200 0) + pin(0 3) + pin(1 5) + pin(2 16) + pin(3 3) + pin(4 4) + pin(5 16) + ) + circuit(9 INVX1 location(6000 0) + pin(0 3) + pin(1 6) + pin(2 16) + pin(3 3) + pin(4 5) + pin(5 16) + ) + circuit(10 INVX1 location(7800 0) + pin(0 3) + pin(1 7) + pin(2 16) + pin(3 3) + pin(4 6) + pin(5 16) + ) + circuit(11 INVX1 location(9600 0) + pin(0 3) + pin(1 8) + pin(2 16) + pin(3 3) + pin(4 7) + pin(5 16) + ) + circuit(12 INVX1 location(11400 0) + pin(0 3) + pin(1 9) + pin(2 16) + pin(3 3) + pin(4 8) + pin(5 16) + ) + circuit(13 INVX1 location(13200 0) + pin(0 3) + pin(1 10) + pin(2 16) + pin(3 3) + pin(4 9) + pin(5 16) + ) + circuit(14 INVX1 location(15000 0) + pin(0 3) + pin(1 11) + pin(2 16) + pin(3 3) + pin(4 10) + pin(5 16) + ) + circuit(15 INVX1 location(16800 0) + pin(0 3) + pin(1 12) + pin(2 16) + pin(3 3) + pin(4 11) + pin(5 16) + ) + circuit(16 INVX1 location(18600 0) + pin(0 3) + pin(1 13) + pin(2 16) + pin(3 3) + pin(4 12) + pin(5 16) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + net(16 name($1.1)) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Devices and their connections + device(1 PMOS + name($1.$1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 6) + terminal(G 4) + terminal(D 2) + terminal(B 2) + ) + device(2 PMOS + name($1.$2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 3) + terminal(D 6) + terminal(B 2) + ) + device(3 NMOS + name($1.$3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 4) + terminal(D 16) + terminal(B 1) + ) + device(4 NMOS + name($1.$4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 16) + terminal(G 3) + terminal(D 6) + terminal(B 1) + ) + + # Subcircuits and their connections + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(1 2 match) + device(2 1 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(15 16 match) + net(4 6 match) + net(13 15 match) + net(5 7 match) + net(6 8 match) + net(7 9 match) + net(8 10 match) + net(9 11 match) + net(10 12 match) + net(11 13 match) + net(12 14 match) + net(2 4 match) + net(1 3 match) + net(14 5 match) + net(3 2 match) + net(16 1 match) + pin(1 3 match) + pin(0 2 match) + pin(3 4 match) + pin(2 1 match) + pin(4 0 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + circuit(8 2 match) + circuit(9 3 match) + circuit(10 4 match) + circuit(11 5 match) + circuit(12 6 match) + circuit(13 7 match) + circuit(14 8 match) + circuit(15 9 match) + circuit(16 10 match) + circuit(2 11 match) + circuit(1 12 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_blackboxing.lvsdb b/testdata/lvs/ringo_simple_blackboxing.lvsdb index 0e9ead554..0ab36f522 100644 --- a/testdata/lvs/ringo_simple_blackboxing.lvsdb +++ b/testdata/lvs/ringo_simple_blackboxing.lvsdb @@ -530,13 +530,13 @@ xref( net(8 4 match) net(5 3 match) net(7 5 match) - net(6 1 warning) - net(9 2 warning) + net(6 2 warning) + net(9 1 warning) pin(3 3 match) pin(0 2 match) pin(2 4 match) - pin(1 0 match) - pin(4 1 match) + pin(1 1 match) + pin(4 0 match) circuit(2 2 match) circuit(3 3 match) circuit(17 4 match) diff --git a/testdata/lvs/ringo_simple_dmos.cir b/testdata/lvs/ringo_simple_dmos.cir new file mode 100644 index 000000000..d517e69ba --- /dev/null +++ b/testdata/lvs/ringo_simple_dmos.cir @@ -0,0 +1,83 @@ +* Extracted by KLayout + +* cell RINGO +* pin FB +* pin VDD +* pin OUT +* pin ENABLE +* pin VSS +.SUBCKT RINGO 11 12 13 14 15 +* net 11 FB +* net 12 VDD +* net 13 OUT +* net 14 ENABLE +* net 15 VSS +* cell instance $1 r0 *1 1.8,0 +X$1 12 1 15 12 11 14 15 ND2X1 +* cell instance $2 r0 *1 4.2,0 +X$2 12 2 15 12 1 15 INVX1 +* cell instance $3 r0 *1 6,0 +X$3 12 3 15 12 2 15 INVX1 +* cell instance $4 r0 *1 7.8,0 +X$4 12 4 15 12 3 15 INVX1 +* cell instance $5 r0 *1 9.6,0 +X$5 12 5 15 12 4 15 INVX1 +* cell instance $6 r0 *1 11.4,0 +X$6 12 6 15 12 5 15 INVX1 +* cell instance $7 r0 *1 13.2,0 +X$7 12 7 15 12 6 15 INVX1 +* cell instance $8 r0 *1 15,0 +X$8 12 8 15 12 7 15 INVX1 +* cell instance $9 r0 *1 16.8,0 +X$9 12 9 15 12 8 15 INVX1 +* cell instance $10 r0 *1 18.6,0 +X$10 12 10 15 12 9 15 INVX1 +* cell instance $11 r0 *1 20.4,0 +X$11 12 11 15 12 10 15 INVX1 +* cell instance $12 r0 *1 22.2,0 +X$12 12 13 15 12 11 15 INVX1 +.ENDS RINGO + +* cell INVX1 +* pin VDD +* pin OUT +* pin VSS +* pin +* pin IN +* pin SUBSTRATE +.SUBCKT INVX1 1 2 3 4 5 6 +* net 1 VDD +* net 2 OUT +* net 3 VSS +* net 5 IN +* net 6 SUBSTRATE +* device instance $1 r0 *1 0.85,5.8 PMOS +M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +* device instance $2 r0 *1 0.85,2.135 NMOS +M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +.ENDS INVX1 + +* cell ND2X1 +* pin VDD +* pin OUT +* pin VSS +* pin +* pin B +* pin A +* pin SUBSTRATE +.SUBCKT ND2X1 1 2 3 5 6 7 8 +* net 1 VDD +* net 2 OUT +* net 3 VSS +* net 6 B +* net 7 A +* net 8 SUBSTRATE +* device instance $1 r0 *1 0.85,5.8 PMOS +M$1 1 7 2 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +* device instance $2 r0 *1 1.55,5.8 PMOS +M$2 1 6 2 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +* device instance $3 r0 *1 0.85,2.135 NMOS +M$3 4 7 3 8 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +* device instance $4 r0 *1 1.55,2.135 NMOS +M$4 4 6 2 8 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +.ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_dmos.lvs b/testdata/lvs/ringo_simple_dmos.lvs new file mode 100644 index 000000000..0879f5e1b --- /dev/null +++ b/testdata/lvs/ringo_simple_dmos.lvs @@ -0,0 +1,81 @@ + +source($lvs_test_source, "RINGO") + +report_lvs($lvs_test_target_lvsdb, true) + +target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout") + +schematic("ringo.cir") + +deep + +# Drawing layers + +nwell = input(1, 0) +active = input(2, 0) +pplus = input(3, 0) +nplus = input(4, 0) +poly = input(5, 0) +contact = input(8, 0) +metal1 = input(9, 0) +via1 = input(10, 0) +metal2 = input(11, 0) +source = input(14, 0) + +# Bulk layer for terminal provisioning + +bulk = polygon_layer + +# Computed layers + +active_in_nwell = active & nwell +pactive = active_in_nwell & pplus +pgate = pactive & poly +psd = pactive - pgate +ps = psd & source +pd = psd - source +ntie = active_in_nwell & nplus + +active_outside_nwell = active - nwell +nactive = active_outside_nwell & nplus +ngate = nactive & poly +nsd = nactive - ngate +ns = nsd & source +nd = nsd - source +ptie = active_outside_nwell & pplus + +# Device extraction + +# PMOS transistor device extraction +extract_devices(dmos4("PMOS"), { "S" => ps, "D" => pd, "G" => pgate, "W" => nwell, + "tS" => ps, "tD" => pd, "tG" => poly, "tW" => nwell }) + +# NMOS transistor device extraction +extract_devices(dmos4("NMOS"), { "S" => ns, "D" => nd, "G" => ngate, "W" => bulk, + "tS" => ns, "tD" => nd, "tG" => poly, "tW" => bulk }) + +# Define connectivity for netlist extraction + +# Inter-layer +connect(ps, contact) +connect(pd, contact) +connect(ns, contact) +connect(nd, contact) +connect(poly, contact) +connect(ntie, contact) +connect(nwell, ntie) +connect(ptie, contact) +connect(contact, metal1) +connect(metal1, via1) +connect(via1, metal2) + +# Global +connect_global(bulk, "SUBSTRATE") +connect_global(ptie, "SUBSTRATE") + +# Compare section + +netlist.simplify + +compare + diff --git a/testdata/lvs/ringo_simple_dmos.lvsdb.1 b/testdata/lvs/ringo_simple_dmos.lvsdb.1 new file mode 100644 index 000000000..9e3146d88 --- /dev/null +++ b/testdata/lvs/ringo_simple_dmos.lvsdb.1 @@ -0,0 +1,925 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l4 '1/0') + layer(l5 '5/0') + layer(l10 '8/0') + layer(l13 '9/0') + layer(l14 '10/0') + layer(l15 '11/0') + layer(l9) + layer(l3) + layer(l1) + layer(l11) + layer(l8) + layer(l6) + layer(l12) + + # Mask layer connectivity + connect(l4 l4 l11) + connect(l5 l5 l10) + connect(l10 l5 l10 l13 l3 l1 l11 l8 l6 l12) + connect(l13 l10 l13 l14) + connect(l14 l13 l14 l15) + connect(l15 l14 l15) + connect(l9 l9) + connect(l3 l10 l3) + connect(l1 l10 l1) + connect(l11 l4 l10 l11) + connect(l8 l10 l8) + connect(l6 l10 l6) + connect(l12 l10 l12) + + # Global nets and connectivity + global(l9 SUBSTRATE) + global(l12 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l3 (125 -750) (450 1500)) + ) + terminal(G + rect(l5 (-125 -750) (250 1500)) + ) + terminal(D + rect(l1 (-550 -750) (425 1500)) + ) + terminal(B + rect(l4 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l3 (-575 -750) (450 1500)) + ) + terminal(G + rect(l5 (-125 -750) (250 1500)) + ) + terminal(D + rect(l1 (125 -750) (425 1500)) + ) + terminal(B + rect(l4 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l3 (-550 -750) (425 1500)) + ) + terminal(G + rect(l5 (-125 -750) (250 1500)) + ) + terminal(D + rect(l1 (125 -750) (425 1500)) + ) + terminal(B + rect(l4 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l8 (125 -475) (450 950)) + ) + terminal(G + rect(l5 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (-550 -475) (425 950)) + ) + terminal(B + rect(l9 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l8 (-575 -475) (450 950)) + ) + terminal(G + rect(l5 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l9 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l8 (-550 -475) (425 950)) + ) + terminal(G + rect(l5 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l9 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l10 (1110 5160) (180 180)) + rect(l10 (-180 920) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l13 (-240 -790) (300 1700)) + rect(l13 (-1350 0) (2400 800)) + rect(l13 (-1151 -401) (2 2)) + rect(l3 (-276 -2151) (425 1500)) + rect(l3 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l10 (1810 1770) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (-1580 3760) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (1220 920) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (-180 370) (180 180)) + polygon(l13 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l13 (-110 1390) (300 1400)) + polygon(l13 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l13 (-141 -501) (2 2)) + rect(l13 (-1751 1099) (300 1400)) + rect(l13 (1100 -1700) (300 300)) + rect(l13 (-300 0) (300 1400)) + rect(l1 (-1750 -1450) (425 1500)) + rect(l1 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l10 (410 1770) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-240 -1300) (300 1360)) + rect(l13 (-650 -2160) (2400 800)) + rect(l13 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l8 (975 1660) (425 950)) + rect(l8 (-400 -950) (425 950)) + ) + net(5 + rect(l4 (-100 4500) (2600 3500)) + ) + net(6 name(B) + rect(l5 (1425 2860) (250 1940)) + rect(l5 (-345 -950) (300 300)) + rect(l5 (-205 650) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l10 (-285 1050) (180 180)) + rect(l13 (-71 -91) (2 2)) + rect(l13 (-171 -151) (300 300)) + ) + net(7 name(A) + rect(l5 (725 2860) (250 1940)) + rect(l5 (-325 -1850) (300 300)) + rect(l5 (-225 1550) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l10 (-265 150) (180 180)) + rect(l13 (-91 -91) (2 2)) + rect(l13 (-151 -151) (300 300)) + ) + net(8 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(5) + pin(6 name(B)) + pin(7 name(A)) + pin(8 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 7) + terminal(D 2) + terminal(B 5) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 6) + terminal(D 2) + terminal(B 5) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 4) + terminal(G 7) + terminal(D 3) + terminal(B 8) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 4) + terminal(G 6) + terminal(D 2) + terminal(B 8) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l10 (410 6260) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l13 (-240 -240) (300 1400)) + rect(l13 (-650 300) (1800 800)) + rect(l13 (-1450 -1100) (300 300)) + rect(l13 (299 399) (2 2)) + rect(l3 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l10 (1110 5160) (180 180)) + rect(l10 (-180 920) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (-180 -4120) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-240 -790) (300 4790)) + rect(l13 (-151 -2501) (2 2)) + rect(l1 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l10 (410 1770) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-240 -1300) (300 1360)) + rect(l13 (-650 -2160) (1800 800)) + rect(l13 (-851 -401) (2 2)) + rect(l8 (-651 859) (425 950)) + ) + net(4 + rect(l4 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l5 (725 2860) (250 1940)) + rect(l5 (-525 -1850) (300 300)) + rect(l5 (-25 1550) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l10 (-465 150) (180 180)) + rect(l13 (-91 -91) (2 2)) + rect(l13 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l10 (4710 3010) (180 180)) + rect(l13 (-850 -240) (610 300)) + ) + net(2 + rect(l10 (6510 3010) (180 180)) + rect(l13 (-1140 -240) (900 300)) + ) + net(3 + rect(l10 (8310 3010) (180 180)) + rect(l13 (-1140 -240) (900 300)) + ) + net(4 + rect(l10 (10110 3010) (180 180)) + rect(l13 (-1140 -240) (900 300)) + ) + net(5 + rect(l10 (11910 3010) (180 180)) + rect(l13 (-1140 -240) (900 300)) + ) + net(6 + rect(l10 (13710 3010) (180 180)) + rect(l13 (-1140 -240) (900 300)) + ) + net(7 + rect(l10 (15510 3010) (180 180)) + rect(l13 (-1140 -240) (900 300)) + ) + net(8 + rect(l10 (17310 3010) (180 180)) + rect(l13 (-1140 -240) (900 300)) + ) + net(9 + rect(l10 (19110 3010) (180 180)) + rect(l13 (-1140 -240) (900 300)) + ) + net(10 + rect(l10 (20910 3010) (180 180)) + rect(l13 (-1140 -240) (900 300)) + ) + net(11 name(FB) + rect(l10 (22710 3010) (180 180)) + rect(l10 (-19700 720) (180 180)) + rect(l13 (18380 -1140) (900 300)) + rect(l13 (-19530 590) (320 320)) + rect(l13 (17820 -320) (320 320)) + rect(l14 (-18400 -260) (200 200)) + rect(l14 (17940 -200) (200 200)) + rect(l15 (-18040 -300) (17740 400)) + rect(l15 (-17921 -201) (2 2)) + rect(l15 (-221 -201) (400 400)) + rect(l15 (17740 -400) (400 400)) + ) + net(12 name(VDD) + rect(l4 (500 4500) (1400 3500)) + rect(l4 (-1900 -3500) (600 3500)) + rect(l4 (23300 -3500) (1400 3500)) + rect(l4 (-100 -3500) (600 3500)) + rect(l10 (-24690 -1240) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (23220 370) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l13 (-21741 859) (2 2)) + rect(l13 (-2351 -451) (1200 800)) + rect(l13 (-750 -1450) (300 1400)) + rect(l13 (-101 -351) (2 2)) + rect(l13 (-1251 -401) (600 800)) + rect(l13 (23400 -800) (1200 800)) + rect(l13 (-750 -1450) (300 1400)) + rect(l13 (-101 -351) (2 2)) + rect(l13 (549 -401) (600 800)) + rect(l11 (-24850 -1500) (500 1500)) + rect(l11 (22900 -1500) (500 1500)) + ) + net(13 name(OUT) + rect(l13 (23440 3840) (320 320)) + rect(l14 (-260 -260) (200 200)) + rect(l15 (-101 -101) (2 2)) + rect(l15 (-201 -201) (400 400)) + ) + net(14 name(ENABLE) + rect(l10 (2510 3010) (180 180)) + rect(l13 (-250 -250) (320 320)) + rect(l14 (-260 -260) (200 200)) + rect(l15 (-101 -101) (2 2)) + rect(l15 (-201 -201) (400 400)) + ) + net(15 name(VSS) + rect(l10 (1110 1610) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (23220 370) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-21741 -391) (2 2)) + rect(l13 (-1901 -401) (300 1400)) + rect(l13 (-750 -1450) (1200 800)) + rect(l13 (-551 -401) (2 2)) + rect(l13 (-1251 -401) (600 800)) + rect(l13 (23850 -750) (300 1400)) + rect(l13 (-750 -1450) (1200 800)) + rect(l13 (-551 -401) (2 2)) + rect(l13 (549 -401) (600 800)) + rect(l12 (-24850 -800) (500 1500)) + rect(l12 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(11 name(FB)) + pin(12 name(VDD)) + pin(13 name(OUT)) + pin(14 name(ENABLE)) + pin(15 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 12) + pin(1 1) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 14) + pin(6 15) + ) + circuit(2 INVX1 location(4200 0) + pin(0 12) + pin(1 2) + pin(2 15) + pin(3 12) + pin(4 1) + pin(5 15) + ) + circuit(3 INVX1 location(6000 0) + pin(0 12) + pin(1 3) + pin(2 15) + pin(3 12) + pin(4 2) + pin(5 15) + ) + circuit(4 INVX1 location(7800 0) + pin(0 12) + pin(1 4) + pin(2 15) + pin(3 12) + pin(4 3) + pin(5 15) + ) + circuit(5 INVX1 location(9600 0) + pin(0 12) + pin(1 5) + pin(2 15) + pin(3 12) + pin(4 4) + pin(5 15) + ) + circuit(6 INVX1 location(11400 0) + pin(0 12) + pin(1 6) + pin(2 15) + pin(3 12) + pin(4 5) + pin(5 15) + ) + circuit(7 INVX1 location(13200 0) + pin(0 12) + pin(1 7) + pin(2 15) + pin(3 12) + pin(4 6) + pin(5 15) + ) + circuit(8 INVX1 location(15000 0) + pin(0 12) + pin(1 8) + pin(2 15) + pin(3 12) + pin(4 7) + pin(5 15) + ) + circuit(9 INVX1 location(16800 0) + pin(0 12) + pin(1 9) + pin(2 15) + pin(3 12) + pin(4 8) + pin(5 15) + ) + circuit(10 INVX1 location(18600 0) + pin(0 12) + pin(1 10) + pin(2 15) + pin(3 12) + pin(4 9) + pin(5 15) + ) + circuit(11 INVX1 location(20400 0) + pin(0 12) + pin(1 11) + pin(2 15) + pin(3 12) + pin(4 10) + pin(5 15) + ) + circuit(12 INVX1 location(22200 0) + pin(0 12) + pin(1 13) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 15) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 nomatch + xref( + net(4 8 mismatch) + net(5 4 mismatch) + net(7 6 match) + net(6 5 match) + net(2 2 mismatch) + net(8 7 mismatch) + net(1 1 mismatch) + net(3 3 mismatch) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(4 4 match) + device(3 3 mismatch) + device(2 2 match) + device(1 1 mismatch) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(10 15 match) + net(2 7 match) + net(3 8 match) + net(4 9 match) + net(5 10 match) + net(6 11 match) + net(7 12 match) + net(8 13 match) + net(9 14 match) + net(14 4 match) + net(11 3 match) + net(13 5 match) + net(12 2 match) + net(15 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(4 4 match) + circuit(5 5 match) + circuit(6 6 match) + circuit(7 7 match) + circuit(8 8 match) + circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_dmos.lvsdb.2 b/testdata/lvs/ringo_simple_dmos.lvsdb.2 new file mode 100644 index 000000000..4256ead4a --- /dev/null +++ b/testdata/lvs/ringo_simple_dmos.lvsdb.2 @@ -0,0 +1,925 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l4 '1/0') + layer(l5 '5/0') + layer(l10 '8/0') + layer(l13 '9/0') + layer(l14 '10/0') + layer(l15 '11/0') + layer(l9) + layer(l3) + layer(l1) + layer(l11) + layer(l8) + layer(l6) + layer(l12) + + # Mask layer connectivity + connect(l4 l4 l11) + connect(l5 l5 l10) + connect(l10 l5 l10 l13 l3 l1 l11 l8 l6 l12) + connect(l13 l10 l13 l14) + connect(l14 l13 l14 l15) + connect(l15 l14 l15) + connect(l9 l9) + connect(l3 l10 l3) + connect(l1 l10 l1) + connect(l11 l4 l10 l11) + connect(l8 l10 l8) + connect(l6 l10 l6) + connect(l12 l10 l12) + + # Global nets and connectivity + global(l9 SUBSTRATE) + global(l12 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l3 (125 -750) (450 1500)) + ) + terminal(G + rect(l5 (-125 -750) (250 1500)) + ) + terminal(D + rect(l1 (-550 -750) (425 1500)) + ) + terminal(B + rect(l4 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l3 (-575 -750) (450 1500)) + ) + terminal(G + rect(l5 (-125 -750) (250 1500)) + ) + terminal(D + rect(l1 (125 -750) (425 1500)) + ) + terminal(B + rect(l4 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l3 (-550 -750) (425 1500)) + ) + terminal(G + rect(l5 (-125 -750) (250 1500)) + ) + terminal(D + rect(l1 (125 -750) (425 1500)) + ) + terminal(B + rect(l4 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l8 (125 -475) (450 950)) + ) + terminal(G + rect(l5 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (-550 -475) (425 950)) + ) + terminal(B + rect(l9 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l8 (-575 -475) (450 950)) + ) + terminal(G + rect(l5 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l9 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l8 (-550 -475) (425 950)) + ) + terminal(G + rect(l5 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l9 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l10 (1110 5160) (180 180)) + rect(l10 (-180 920) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l13 (-240 -790) (300 1700)) + rect(l13 (-1350 0) (2400 800)) + rect(l13 (-1151 -401) (2 2)) + rect(l3 (-251 -2151) (425 1500)) + rect(l3 (-450 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l10 (1810 1770) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (-1580 3760) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (1220 920) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (-180 370) (180 180)) + polygon(l13 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l13 (-110 1390) (300 1400)) + polygon(l13 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l13 (-141 -501) (2 2)) + rect(l13 (-1751 1099) (300 1400)) + rect(l13 (1100 -1700) (300 300)) + rect(l13 (-300 0) (300 1400)) + rect(l1 (-1750 -1450) (425 1500)) + rect(l1 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l10 (410 1770) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-240 -1300) (300 1360)) + rect(l13 (-650 -2160) (2400 800)) + rect(l13 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l8 (1000 1660) (425 950)) + rect(l8 (-450 -950) (425 950)) + ) + net(5 + rect(l4 (-100 4500) (2600 3500)) + ) + net(6 name(B) + rect(l5 (1425 2860) (250 1940)) + rect(l5 (-345 -950) (300 300)) + rect(l5 (-205 650) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l10 (-285 1050) (180 180)) + rect(l13 (-71 -91) (2 2)) + rect(l13 (-171 -151) (300 300)) + ) + net(7 name(A) + rect(l5 (725 2860) (250 1940)) + rect(l5 (-325 -1850) (300 300)) + rect(l5 (-225 1550) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l10 (-265 150) (180 180)) + rect(l13 (-91 -91) (2 2)) + rect(l13 (-151 -151) (300 300)) + ) + net(8 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(5) + pin(6 name(B)) + pin(7 name(A)) + pin(8 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 7) + terminal(D 2) + terminal(B 5) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 6) + terminal(D 2) + terminal(B 5) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 4) + terminal(G 7) + terminal(D 3) + terminal(B 8) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 4) + terminal(G 6) + terminal(D 2) + terminal(B 8) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l10 (410 6260) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l13 (-240 -240) (300 1400)) + rect(l13 (-650 300) (1800 800)) + rect(l13 (-1450 -1100) (300 300)) + rect(l13 (299 399) (2 2)) + rect(l3 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l10 (1110 5160) (180 180)) + rect(l10 (-180 920) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (-180 -4120) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-240 -790) (300 4790)) + rect(l13 (-151 -2501) (2 2)) + rect(l1 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l10 (410 1770) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-240 -1300) (300 1360)) + rect(l13 (-650 -2160) (1800 800)) + rect(l13 (-851 -401) (2 2)) + rect(l8 (-651 859) (425 950)) + ) + net(4 + rect(l4 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l5 (725 2860) (250 1940)) + rect(l5 (-525 -1850) (300 300)) + rect(l5 (-25 1550) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l10 (-465 150) (180 180)) + rect(l13 (-91 -91) (2 2)) + rect(l13 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l10 (4710 3010) (180 180)) + rect(l13 (-850 -240) (610 300)) + ) + net(2 + rect(l10 (6510 3010) (180 180)) + rect(l13 (-1140 -240) (900 300)) + ) + net(3 + rect(l10 (8310 3010) (180 180)) + rect(l13 (-1140 -240) (900 300)) + ) + net(4 + rect(l10 (10110 3010) (180 180)) + rect(l13 (-1140 -240) (900 300)) + ) + net(5 + rect(l10 (11910 3010) (180 180)) + rect(l13 (-1140 -240) (900 300)) + ) + net(6 + rect(l10 (13710 3010) (180 180)) + rect(l13 (-1140 -240) (900 300)) + ) + net(7 + rect(l10 (15510 3010) (180 180)) + rect(l13 (-1140 -240) (900 300)) + ) + net(8 + rect(l10 (17310 3010) (180 180)) + rect(l13 (-1140 -240) (900 300)) + ) + net(9 + rect(l10 (19110 3010) (180 180)) + rect(l13 (-1140 -240) (900 300)) + ) + net(10 + rect(l10 (20910 3010) (180 180)) + rect(l13 (-1140 -240) (900 300)) + ) + net(11 name(FB) + rect(l10 (22710 3010) (180 180)) + rect(l10 (-19700 720) (180 180)) + rect(l13 (18380 -1140) (900 300)) + rect(l13 (-19530 590) (320 320)) + rect(l13 (17820 -320) (320 320)) + rect(l14 (-18400 -260) (200 200)) + rect(l14 (17940 -200) (200 200)) + rect(l15 (-18040 -300) (17740 400)) + rect(l15 (-17921 -201) (2 2)) + rect(l15 (-221 -201) (400 400)) + rect(l15 (17740 -400) (400 400)) + ) + net(12 name(VDD) + rect(l4 (500 4500) (1400 3500)) + rect(l4 (-1900 -3500) (600 3500)) + rect(l4 (23300 -3500) (1400 3500)) + rect(l4 (-100 -3500) (600 3500)) + rect(l10 (-24690 -1240) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (23220 370) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l13 (-21741 859) (2 2)) + rect(l13 (-2351 -451) (1200 800)) + rect(l13 (-750 -1450) (300 1400)) + rect(l13 (-101 -351) (2 2)) + rect(l13 (-1251 -401) (600 800)) + rect(l13 (23400 -800) (1200 800)) + rect(l13 (-750 -1450) (300 1400)) + rect(l13 (-101 -351) (2 2)) + rect(l13 (549 -401) (600 800)) + rect(l11 (-24850 -1500) (500 1500)) + rect(l11 (22900 -1500) (500 1500)) + ) + net(13 name(OUT) + rect(l13 (23440 3840) (320 320)) + rect(l14 (-260 -260) (200 200)) + rect(l15 (-101 -101) (2 2)) + rect(l15 (-201 -201) (400 400)) + ) + net(14 name(ENABLE) + rect(l10 (2510 3010) (180 180)) + rect(l13 (-250 -250) (320 320)) + rect(l14 (-260 -260) (200 200)) + rect(l15 (-101 -101) (2 2)) + rect(l15 (-201 -201) (400 400)) + ) + net(15 name(VSS) + rect(l10 (1110 1610) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (23220 370) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-21741 -391) (2 2)) + rect(l13 (-1901 -401) (300 1400)) + rect(l13 (-750 -1450) (1200 800)) + rect(l13 (-551 -401) (2 2)) + rect(l13 (-1251 -401) (600 800)) + rect(l13 (23850 -750) (300 1400)) + rect(l13 (-750 -1450) (1200 800)) + rect(l13 (-551 -401) (2 2)) + rect(l13 (549 -401) (600 800)) + rect(l12 (-24850 -800) (500 1500)) + rect(l12 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(11 name(FB)) + pin(12 name(VDD)) + pin(13 name(OUT)) + pin(14 name(ENABLE)) + pin(15 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 12) + pin(1 1) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 14) + pin(6 15) + ) + circuit(2 INVX1 location(4200 0) + pin(0 12) + pin(1 2) + pin(2 15) + pin(3 12) + pin(4 1) + pin(5 15) + ) + circuit(3 INVX1 location(6000 0) + pin(0 12) + pin(1 3) + pin(2 15) + pin(3 12) + pin(4 2) + pin(5 15) + ) + circuit(4 INVX1 location(7800 0) + pin(0 12) + pin(1 4) + pin(2 15) + pin(3 12) + pin(4 3) + pin(5 15) + ) + circuit(5 INVX1 location(9600 0) + pin(0 12) + pin(1 5) + pin(2 15) + pin(3 12) + pin(4 4) + pin(5 15) + ) + circuit(6 INVX1 location(11400 0) + pin(0 12) + pin(1 6) + pin(2 15) + pin(3 12) + pin(4 5) + pin(5 15) + ) + circuit(7 INVX1 location(13200 0) + pin(0 12) + pin(1 7) + pin(2 15) + pin(3 12) + pin(4 6) + pin(5 15) + ) + circuit(8 INVX1 location(15000 0) + pin(0 12) + pin(1 8) + pin(2 15) + pin(3 12) + pin(4 7) + pin(5 15) + ) + circuit(9 INVX1 location(16800 0) + pin(0 12) + pin(1 9) + pin(2 15) + pin(3 12) + pin(4 8) + pin(5 15) + ) + circuit(10 INVX1 location(18600 0) + pin(0 12) + pin(1 10) + pin(2 15) + pin(3 12) + pin(4 9) + pin(5 15) + ) + circuit(11 INVX1 location(20400 0) + pin(0 12) + pin(1 11) + pin(2 15) + pin(3 12) + pin(4 10) + pin(5 15) + ) + circuit(12 INVX1 location(22200 0) + pin(0 12) + pin(1 13) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 15) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 nomatch + xref( + net(4 8 mismatch) + net(5 4 mismatch) + net(7 6 match) + net(6 5 match) + net(2 2 mismatch) + net(8 7 mismatch) + net(1 1 mismatch) + net(3 3 mismatch) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(4 4 match) + device(3 3 mismatch) + device(2 2 match) + device(1 1 mismatch) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(10 15 match) + net(2 7 match) + net(3 8 match) + net(4 9 match) + net(5 10 match) + net(6 11 match) + net(7 12 match) + net(8 13 match) + net(9 14 match) + net(14 4 match) + net(11 3 match) + net(13 5 match) + net(12 2 match) + net(15 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(4 4 match) + circuit(5 5 match) + circuit(6 6 match) + circuit(7 7 match) + circuit(8 8 match) + circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_dummy_device.cir b/testdata/lvs/ringo_simple_dummy_device.cir new file mode 100644 index 000000000..9b5fe15e2 --- /dev/null +++ b/testdata/lvs/ringo_simple_dummy_device.cir @@ -0,0 +1,85 @@ +* Extracted by KLayout + +* cell RINGO +* pin FB +* pin VDD +* pin OUT +* pin ENABLE +* pin VSS +.SUBCKT RINGO 12 13 14 15 16 +* net 12 FB +* net 13 VDD +* net 14 OUT +* net 15 ENABLE +* net 16 VSS +* cell instance $3 r0 *1 1.8,0 +X$3 13 2 16 13 12 15 16 ND2X1 +* cell instance $4 r0 *1 4.2,0 +X$4 13 3 16 13 2 16 INVX1 +* cell instance $5 r0 *1 6,0 +X$5 13 4 16 13 3 16 INVX1 +* cell instance $6 r0 *1 7.8,0 +X$6 13 5 16 13 4 16 INVX1 +* cell instance $7 r0 *1 9.6,0 +X$7 13 6 16 13 5 16 INVX1 +* cell instance $8 r0 *1 11.4,0 +X$8 13 7 16 13 6 16 INVX1 +* cell instance $9 r0 *1 13.2,0 +X$9 13 8 16 13 7 16 INVX1 +* cell instance $10 r0 *1 15,0 +X$10 13 9 16 13 8 16 INVX1 +* cell instance $11 r0 *1 16.8,0 +X$11 13 10 16 13 9 16 INVX1 +* cell instance $12 r0 *1 18.6,0 +X$12 13 11 16 13 10 16 INVX1 +* cell instance $13 r0 *1 20.4,0 +X$13 13 12 16 13 11 16 INVX1 +* cell instance $14 r0 *1 22.2,0 +X$14 13 14 16 13 12 16 INVX1 +* device instance $1 r0 *1 26.45,2.075 NMOS +M$1 16 1 16 16 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +.ENDS RINGO + +* cell INVX1 +* pin VDD +* pin OUT +* pin VSS +* pin +* pin IN +* pin SUBSTRATE +.SUBCKT INVX1 1 2 3 4 5 6 +* net 1 VDD +* net 2 OUT +* net 3 VSS +* net 5 IN +* net 6 SUBSTRATE +* device instance $1 r0 *1 0.85,5.8 PMOS +M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +* device instance $2 r0 *1 0.85,2.135 NMOS +M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +.ENDS INVX1 + +* cell ND2X1 +* pin VDD +* pin OUT +* pin VSS +* pin +* pin B +* pin A +* pin SUBSTRATE +.SUBCKT ND2X1 1 2 3 4 5 6 7 +* net 1 VDD +* net 2 OUT +* net 3 VSS +* net 5 B +* net 6 A +* net 7 SUBSTRATE +* device instance $1 r0 *1 0.85,5.8 PMOS +M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +* device instance $2 r0 *1 1.55,5.8 PMOS +M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +* device instance $3 r0 *1 0.85,2.135 NMOS +M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +* device instance $4 r0 *1 1.55,2.135 NMOS +M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +.ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_dummy_device.lvs b/testdata/lvs/ringo_simple_dummy_device.lvs new file mode 100644 index 000000000..a33340a2d --- /dev/null +++ b/testdata/lvs/ringo_simple_dummy_device.lvs @@ -0,0 +1,74 @@ + +source($lvs_test_source, "RINGO") + +report_lvs($lvs_test_target_lvsdb, true) + +target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout") + +schematic("ringo_dummy_device.cir") + +deep + +# Drawing layers + +nwell = input(1, 0) +active = input(2, 0) +pplus = input(3, 0) +nplus = input(4, 0) +poly = input(5, 0) +contact = input(8, 0) +metal1 = input(9, 0) +via1 = input(10, 0) +metal2 = input(11, 0) + +# Bulk layer for terminal provisioning + +bulk = polygon_layer + +# Computed layers + +active_in_nwell = active & nwell +pactive = active_in_nwell & pplus +pgate = pactive & poly +psd = pactive - pgate +ntie = active_in_nwell & nplus + +active_outside_nwell = active - nwell +nactive = active_outside_nwell & nplus +ngate = nactive & poly +nsd = nactive - ngate +ptie = active_outside_nwell & pplus + +# Device extraction + +# PMOS transistor device extraction +extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell, + "tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell }) + +# NMOS transistor device extraction +extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk, + "tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk }) + +# Define connectivity for netlist extraction + +# Inter-layer +connect(psd, contact) +connect(nsd, contact) +connect(poly, contact) +connect(ntie, contact) +connect(nwell, ntie) +connect(ptie, contact) +connect(contact, metal1) +connect(metal1, via1) +connect(via1, metal2) + +# Global +connect_global(bulk, "SUBSTRATE") +connect_global(ptie, "SUBSTRATE") + +# Compare section + +netlist.simplify + +compare + diff --git a/testdata/lvs/ringo_simple_dummy_device.lvsdb.1 b/testdata/lvs/ringo_simple_dummy_device.lvsdb.1 new file mode 100644 index 000000000..ee46022fe --- /dev/null +++ b/testdata/lvs/ringo_simple_dummy_device.lvsdb.1 @@ -0,0 +1,1028 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-1750 -1450) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS$1 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$2 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (27600 7650)) + + # Nets with their geometries + net(1 + rect(l4 (26050 2800) (525 550)) + rect(l4 (-525 -300) (300 300)) + rect(l4 (-25 -2000) (250 1450)) + rect(l8 (-465 310) (180 180)) + rect(l11 (-240 -240) (300 300)) + ) + net(2 + rect(l8 (4710 3010) (180 180)) + rect(l11 (-850 -240) (610 300)) + rect(l2 (-2550 1800) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 + rect(l8 (6510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(4 + rect(l8 (8310 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(5 + rect(l8 (10110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(6 + rect(l8 (11910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(7 + rect(l8 (13710 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(8 + rect(l8 (15510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(9 + rect(l8 (17310 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(10 + rect(l8 (19110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(11 + rect(l8 (20910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(12 name(FB) + rect(l8 (22710 3010) (180 180)) + rect(l8 (-19700 720) (180 180)) + rect(l11 (18380 -1140) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(13 name(VDD) + rect(l3 (500 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l3 (0 -3500) (600 3500)) + rect(l3 (0 -3500) (600 3500)) + rect(l3 (0 -3500) (600 3500)) + rect(l8 (-26490 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-21741 859) (2 2)) + rect(l11 (-2351 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l2 (-24825 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l9 (-21975 -450) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(14 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + rect(l2 (-625 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(15 name(ENABLE) + rect(l8 (2510 3010) (180 180)) + rect(l11 (-250 -250) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(16 name(VSS) + rect(l8 (26010 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (520 -730) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-25780 -890) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (1260 -40) (300 1360)) + rect(l11 (400 -1360) (300 1360)) + rect(l11 (-24001 -1711) (2 2)) + rect(l11 (-1901 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l6 (-25500 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (2975 -1010) (425 950)) + rect(l6 (250 -950) (425 950)) + rect(l10 (-26050 -2150) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(12 name(FB)) + pin(13 name(VDD)) + pin(14 name(OUT)) + pin(15 name(ENABLE)) + pin(16 name(VSS)) + + # Devices and their connections + device(1 D$NMOS + location(26450 2075) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 16) + terminal(G 1) + terminal(D 16) + terminal(B 16) + ) + + # Subcircuits and their connections + circuit(3 ND2X1 location(1800 0) + pin(0 13) + pin(1 2) + pin(2 16) + pin(3 13) + pin(4 12) + pin(5 15) + pin(6 16) + ) + circuit(4 INVX1 location(4200 0) + pin(0 13) + pin(1 3) + pin(2 16) + pin(3 13) + pin(4 2) + pin(5 16) + ) + circuit(5 INVX1 location(6000 0) + pin(0 13) + pin(1 4) + pin(2 16) + pin(3 13) + pin(4 3) + pin(5 16) + ) + circuit(6 INVX1 location(7800 0) + pin(0 13) + pin(1 5) + pin(2 16) + pin(3 13) + pin(4 4) + pin(5 16) + ) + circuit(7 INVX1 location(9600 0) + pin(0 13) + pin(1 6) + pin(2 16) + pin(3 13) + pin(4 5) + pin(5 16) + ) + circuit(8 INVX1 location(11400 0) + pin(0 13) + pin(1 7) + pin(2 16) + pin(3 13) + pin(4 6) + pin(5 16) + ) + circuit(9 INVX1 location(13200 0) + pin(0 13) + pin(1 8) + pin(2 16) + pin(3 13) + pin(4 7) + pin(5 16) + ) + circuit(10 INVX1 location(15000 0) + pin(0 13) + pin(1 9) + pin(2 16) + pin(3 13) + pin(4 8) + pin(5 16) + ) + circuit(11 INVX1 location(16800 0) + pin(0 13) + pin(1 10) + pin(2 16) + pin(3 13) + pin(4 9) + pin(5 16) + ) + circuit(12 INVX1 location(18600 0) + pin(0 13) + pin(1 11) + pin(2 16) + pin(3 13) + pin(4 10) + pin(5 16) + ) + circuit(13 INVX1 location(20400 0) + pin(0 13) + pin(1 12) + pin(2 16) + pin(3 13) + pin(4 11) + pin(5 16) + ) + circuit(14 INVX1 location(22200 0) + pin(0 13) + pin(1 14) + pin(2 16) + pin(3 13) + pin(4 12) + pin(5 16) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(NMOS MOS4) + class(PMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + net(16 name(DUMMY)) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Devices and their connections + device(1 NMOS + name($1) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 16) + terminal(D 1) + terminal(B 1) + ) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(2 6 match) + net(11 15 match) + net(3 7 match) + net(4 8 match) + net(5 9 match) + net(6 10 match) + net(7 11 match) + net(8 12 match) + net(9 13 match) + net(10 14 match) + net(1 16 match) + net(15 4 match) + net(12 3 match) + net(14 5 match) + net(13 2 match) + net(16 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + device(1 1 match) + circuit(4 2 match) + circuit(5 3 match) + circuit(6 4 match) + circuit(7 5 match) + circuit(8 6 match) + circuit(9 7 match) + circuit(10 8 match) + circuit(11 9 match) + circuit(12 10 match) + circuit(13 11 match) + circuit(14 12 match) + circuit(3 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_dummy_device.lvsdb.2 b/testdata/lvs/ringo_simple_dummy_device.lvsdb.2 new file mode 100644 index 000000000..f4780ff2d --- /dev/null +++ b/testdata/lvs/ringo_simple_dummy_device.lvsdb.2 @@ -0,0 +1,1028 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS$1 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$2 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (27600 7650)) + + # Nets with their geometries + net(1 + rect(l4 (26050 2800) (525 550)) + rect(l4 (-525 -300) (300 300)) + rect(l4 (-25 -2000) (250 1450)) + rect(l8 (-465 310) (180 180)) + rect(l11 (-240 -240) (300 300)) + ) + net(2 + rect(l8 (4710 3010) (180 180)) + rect(l11 (-850 -240) (610 300)) + rect(l2 (-1175 1800) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) + ) + net(3 + rect(l8 (6510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(4 + rect(l8 (8310 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(5 + rect(l8 (10110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(6 + rect(l8 (11910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(7 + rect(l8 (13710 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(8 + rect(l8 (15510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(9 + rect(l8 (17310 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(10 + rect(l8 (19110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(11 + rect(l8 (20910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(12 name(FB) + rect(l8 (22710 3010) (180 180)) + rect(l8 (-19700 720) (180 180)) + rect(l11 (18380 -1140) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(13 name(VDD) + rect(l3 (500 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l3 (0 -3500) (600 3500)) + rect(l3 (0 -3500) (600 3500)) + rect(l3 (0 -3500) (600 3500)) + rect(l8 (-26490 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-21741 859) (2 2)) + rect(l11 (-2351 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l2 (-24825 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l9 (-21975 -450) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(14 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + rect(l2 (-625 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(15 name(ENABLE) + rect(l8 (2510 3010) (180 180)) + rect(l11 (-250 -250) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(16 name(VSS) + rect(l8 (26010 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (520 -730) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-25780 -890) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (1260 -40) (300 1360)) + rect(l11 (400 -1360) (300 1360)) + rect(l11 (-24001 -1711) (2 2)) + rect(l11 (-1901 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l6 (-25500 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (3650 -1010) (425 950)) + rect(l6 (-1100 -950) (425 950)) + rect(l10 (-25375 -2150) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(12 name(FB)) + pin(13 name(VDD)) + pin(14 name(OUT)) + pin(15 name(ENABLE)) + pin(16 name(VSS)) + + # Devices and their connections + device(1 D$NMOS + location(26450 2075) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 16) + terminal(G 1) + terminal(D 16) + terminal(B 16) + ) + + # Subcircuits and their connections + circuit(3 ND2X1 location(1800 0) + pin(0 13) + pin(1 2) + pin(2 16) + pin(3 13) + pin(4 12) + pin(5 15) + pin(6 16) + ) + circuit(4 INVX1 location(4200 0) + pin(0 13) + pin(1 3) + pin(2 16) + pin(3 13) + pin(4 2) + pin(5 16) + ) + circuit(5 INVX1 location(6000 0) + pin(0 13) + pin(1 4) + pin(2 16) + pin(3 13) + pin(4 3) + pin(5 16) + ) + circuit(6 INVX1 location(7800 0) + pin(0 13) + pin(1 5) + pin(2 16) + pin(3 13) + pin(4 4) + pin(5 16) + ) + circuit(7 INVX1 location(9600 0) + pin(0 13) + pin(1 6) + pin(2 16) + pin(3 13) + pin(4 5) + pin(5 16) + ) + circuit(8 INVX1 location(11400 0) + pin(0 13) + pin(1 7) + pin(2 16) + pin(3 13) + pin(4 6) + pin(5 16) + ) + circuit(9 INVX1 location(13200 0) + pin(0 13) + pin(1 8) + pin(2 16) + pin(3 13) + pin(4 7) + pin(5 16) + ) + circuit(10 INVX1 location(15000 0) + pin(0 13) + pin(1 9) + pin(2 16) + pin(3 13) + pin(4 8) + pin(5 16) + ) + circuit(11 INVX1 location(16800 0) + pin(0 13) + pin(1 10) + pin(2 16) + pin(3 13) + pin(4 9) + pin(5 16) + ) + circuit(12 INVX1 location(18600 0) + pin(0 13) + pin(1 11) + pin(2 16) + pin(3 13) + pin(4 10) + pin(5 16) + ) + circuit(13 INVX1 location(20400 0) + pin(0 13) + pin(1 12) + pin(2 16) + pin(3 13) + pin(4 11) + pin(5 16) + ) + circuit(14 INVX1 location(22200 0) + pin(0 13) + pin(1 14) + pin(2 16) + pin(3 13) + pin(4 12) + pin(5 16) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(NMOS MOS4) + class(PMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + net(16 name(DUMMY)) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Devices and their connections + device(1 NMOS + name($1) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 16) + terminal(D 1) + terminal(B 1) + ) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(2 6 match) + net(11 15 match) + net(3 7 match) + net(4 8 match) + net(5 9 match) + net(6 10 match) + net(7 11 match) + net(8 12 match) + net(9 13 match) + net(10 14 match) + net(1 16 match) + net(15 4 match) + net(12 3 match) + net(14 5 match) + net(13 2 match) + net(16 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + device(1 1 match) + circuit(4 2 match) + circuit(5 3 match) + circuit(6 4 match) + circuit(7 5 match) + circuit(8 6 match) + circuit(9 7 match) + circuit(10 8 match) + circuit(11 9 match) + circuit(12 10 match) + circuit(13 11 match) + circuit(14 12 match) + circuit(3 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_same_device_classes.lvs b/testdata/lvs/ringo_simple_same_device_classes.lvs index da0ec1196..9a2bad4d1 100644 --- a/testdata/lvs/ringo_simple_same_device_classes.lvs +++ b/testdata/lvs/ringo_simple_same_device_classes.lvs @@ -21,6 +21,7 @@ contact = input(8, 0) metal1 = input(9, 0) via1 = input(10, 0) metal2 = input(11, 0) +thickox = input(12, 0) # Bulk layer for terminal provisioning @@ -30,24 +31,42 @@ bulk = polygon_layer active_in_nwell = active & nwell pactive = active_in_nwell & pplus -pgate = pactive & poly -psd = pactive - pgate +pactive_hv = pactive & thickox +pgate_hv = pactive_hv & poly +psd_hv = pactive_hv - pgate_hv +pactive_lv = pactive - thickox +pgate_lv = pactive_lv & poly +psd_lv = pactive_lv - pgate_lv +psd = pactive - poly ntie = active_in_nwell & nplus active_outside_nwell = active - nwell nactive = active_outside_nwell & nplus -ngate = nactive & poly -nsd = nactive - ngate +nactive_hv = nactive & thickox +ngate_hv = nactive_hv & poly +nsd_hv = nactive_hv - ngate_hv +nactive_lv = nactive - thickox +ngate_lv = nactive_lv & poly +nsd_lv = nactive_lv - ngate_lv +nsd = nactive - poly ptie = active_outside_nwell & pplus # Device extraction # PMOS transistor device extraction -extract_devices(mos4("PM"), { "SD" => psd, "G" => pgate, "W" => nwell, - "tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell }) +extract_devices(mos4("PM"), { "SD" => psd_lv, "G" => pgate_lv, "W" => nwell, + "tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell }) # NMOS transistor device extraction -extract_devices(mos4("NM"), { "SD" => nsd, "G" => ngate, "W" => bulk, +extract_devices(mos4("NM"), { "SD" => nsd_lv, "G" => ngate_lv, "W" => bulk, + "tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk }) + +# PMOS transistor device extraction (HV) +extract_devices(mos4("PMHV"), { "SD" => psd_hv, "G" => pgate_hv, "W" => nwell, + "tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell }) + +# NMOS transistor device extraction (HV) +extract_devices(mos4("NMHV"), { "SD" => nsd_hv, "G" => ngate_hv, "W" => bulk, "tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk }) # Define connectivity for netlist extraction @@ -73,6 +92,8 @@ netlist.simplify same_device_classes("PM", "PMOS") same_device_classes("NM", "NMOS") +same_device_classes("PMHV", "PMOSHV") +same_device_classes("NMHV", "NMOSHV") compare diff --git a/testdata/lvs/ringo_simple_same_device_classes.lvsdb.1 b/testdata/lvs/ringo_simple_same_device_classes.lvsdb.1 index 7fc246d6a..bff454e1e 100644 --- a/testdata/lvs/ringo_simple_same_device_classes.lvsdb.1 +++ b/testdata/lvs/ringo_simple_same_device_classes.lvsdb.1 @@ -10,49 +10,51 @@ layout( # Mask layers layer(l3 '1/0') - layer(l4 '5/0') - layer(l8 '8/0') - layer(l11 '9/0') - layer(l12 '10/0') - layer(l13 '11/0') - layer(l7) - layer(l2) + layer(l5 '5/0') + layer(l14 '8/0') + layer(l17 '9/0') + layer(l18 '10/0') + layer(l19 '11/0') + layer(l8) + layer(l4) + layer(l15) layer(l9) - layer(l6) - layer(l10) + layer(l16) # Mask layer connectivity - connect(l3 l3 l9) - connect(l4 l4 l8) - connect(l8 l4 l8 l11 l2 l9 l6 l10) - connect(l11 l8 l11 l12) - connect(l12 l11 l12 l13) - connect(l13 l12 l13) - connect(l7 l7) - connect(l2 l8 l2) - connect(l9 l3 l8 l9) - connect(l6 l8 l6) - connect(l10 l8 l10) + connect(l3 l3 l15) + connect(l5 l5 l14) + connect(l14 l5 l14 l17 l4 l15 l9 l16) + connect(l17 l14 l17 l18) + connect(l18 l17 l18 l19) + connect(l19 l18 l19) + connect(l8 l8) + connect(l4 l14 l4) + connect(l15 l3 l14 l15) + connect(l9 l14 l9) + connect(l16 l14 l16) # Global nets and connectivity - global(l7 SUBSTRATE) - global(l10 SUBSTRATE) + global(l8 SUBSTRATE) + global(l16 SUBSTRATE) # Device class section class(PM MOS4) class(NM MOS4) + class(PMHV MOS4) + class(NMHV MOS4) # Device abstracts section # Device abstracts list the pin shapes of the devices. device(D$PM PM terminal(S - rect(l2 (-550 -750) (425 1500)) + rect(l4 (-550 -750) (425 1500)) ) terminal(G - rect(l4 (-125 -750) (250 1500)) + rect(l5 (-125 -750) (250 1500)) ) terminal(D - rect(l2 (125 -750) (450 1500)) + rect(l4 (125 -750) (450 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -60,13 +62,13 @@ layout( ) device(D$PM$1 PM terminal(S - rect(l2 (-575 -750) (450 1500)) + rect(l4 (-575 -750) (450 1500)) ) terminal(G - rect(l4 (-125 -750) (250 1500)) + rect(l5 (-125 -750) (250 1500)) ) terminal(D - rect(l2 (125 -750) (425 1500)) + rect(l4 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -74,13 +76,13 @@ layout( ) device(D$PM$2 PM terminal(S - rect(l2 (-550 -750) (425 1500)) + rect(l4 (-550 -750) (425 1500)) ) terminal(G - rect(l4 (-125 -750) (250 1500)) + rect(l5 (-125 -750) (250 1500)) ) terminal(D - rect(l2 (125 -750) (425 1500)) + rect(l4 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -88,44 +90,44 @@ layout( ) device(D$NM NM terminal(S - rect(l6 (-550 -475) (425 950)) + rect(l9 (-550 -475) (425 950)) ) terminal(G - rect(l4 (-125 -475) (250 950)) + rect(l5 (-125 -475) (250 950)) ) terminal(D - rect(l6 (125 -475) (450 950)) + rect(l9 (125 -475) (450 950)) ) terminal(B - rect(l7 (-125 -475) (250 950)) + rect(l8 (-125 -475) (250 950)) ) ) device(D$NM$1 NM terminal(S - rect(l6 (-575 -475) (450 950)) + rect(l9 (-575 -475) (450 950)) ) terminal(G - rect(l4 (-125 -475) (250 950)) + rect(l5 (-125 -475) (250 950)) ) terminal(D - rect(l6 (125 -475) (425 950)) + rect(l9 (125 -475) (425 950)) ) terminal(B - rect(l7 (-125 -475) (250 950)) + rect(l8 (-125 -475) (250 950)) ) ) device(D$NM$2 NM terminal(S - rect(l6 (-550 -475) (425 950)) + rect(l9 (-550 -475) (425 950)) ) terminal(G - rect(l4 (-125 -475) (250 950)) + rect(l5 (-125 -475) (250 950)) ) terminal(D - rect(l6 (125 -475) (425 950)) + rect(l9 (125 -475) (425 950)) ) terminal(B - rect(l7 (-125 -475) (250 950)) + rect(l8 (-125 -475) (250 950)) ) ) @@ -138,70 +140,70 @@ layout( # Nets with their geometries net(1 name(VDD) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -790) (300 1700)) - rect(l11 (-1350 0) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l2 (-276 -2151) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) + rect(l14 (1110 5160) (180 180)) + rect(l14 (-180 920) (180 180)) + rect(l14 (-180 -730) (180 180)) + rect(l17 (-240 -790) (300 1700)) + rect(l17 (-1350 0) (2400 800)) + rect(l17 (-1151 -401) (2 2)) + rect(l4 (-276 -2151) (425 1500)) + rect(l4 (-400 -1500) (425 1500)) ) net(2 name(OUT) - rect(l8 (1810 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-1580 3760) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l11 (-110 1390) (300 1400)) - polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l11 (-141 -501) (2 2)) - rect(l11 (-1751 1099) (300 1400)) - rect(l11 (1100 -1700) (300 300)) - rect(l11 (-300 0) (300 1400)) - rect(l2 (-1750 -1450) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (1810 1770) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l14 (-1580 3760) (180 180)) + rect(l14 (-180 -730) (180 180)) + rect(l14 (-180 -730) (180 180)) + rect(l14 (1220 920) (180 180)) + rect(l14 (-180 -1280) (180 180)) + rect(l14 (-180 370) (180 180)) + polygon(l17 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l17 (-110 1390) (300 1400)) + polygon(l17 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l17 (-141 -501) (2 2)) + rect(l17 (-1751 1099) (300 1400)) + rect(l17 (1100 -1700) (300 300)) + rect(l17 (-300 0) (300 1400)) + rect(l4 (-1750 -1450) (425 1500)) + rect(l4 (950 -1500) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l6 (-951 859) (425 950)) + rect(l14 (410 1770) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l17 (-240 -1300) (300 1360)) + rect(l17 (-650 -2160) (2400 800)) + rect(l17 (-1151 -401) (2 2)) + rect(l9 (-951 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2600 3500)) ) net(5 name(B) - rect(l4 (1425 2860) (250 1940)) - rect(l4 (-345 -950) (300 300)) - rect(l4 (-205 650) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-285 1050) (180 180)) - rect(l11 (-71 -91) (2 2)) - rect(l11 (-171 -151) (300 300)) + rect(l5 (1425 2860) (250 1940)) + rect(l5 (-345 -950) (300 300)) + rect(l5 (-205 650) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l14 (-285 1050) (180 180)) + rect(l17 (-71 -91) (2 2)) + rect(l17 (-171 -151) (300 300)) ) net(6 name(A) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-325 -1850) (300 300)) - rect(l4 (-225 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-265 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) + rect(l5 (725 2860) (250 1940)) + rect(l5 (-325 -1850) (300 300)) + rect(l5 (-225 1550) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l14 (-265 150) (180 180)) + rect(l17 (-91 -91) (2 2)) + rect(l17 (-151 -151) (300 300)) ) net(7 name(SUBSTRATE)) net(8 - rect(l6 (975 1660) (425 950)) - rect(l6 (-400 -950) (425 950)) + rect(l9 (975 1660) (425 950)) + rect(l9 (-400 -950) (425 950)) ) # Outgoing pins and their connections to nets @@ -275,46 +277,46 @@ layout( # Nets with their geometries net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (299 399) (2 2)) - rect(l2 (-651 -2151) (425 1500)) + rect(l14 (410 6260) (180 180)) + rect(l14 (-180 -730) (180 180)) + rect(l14 (-180 -730) (180 180)) + rect(l17 (-240 -240) (300 1400)) + rect(l17 (-650 300) (1800 800)) + rect(l17 (-1450 -1100) (300 300)) + rect(l17 (299 399) (2 2)) + rect(l4 (-651 -2151) (425 1500)) ) net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (1110 5160) (180 180)) + rect(l14 (-180 920) (180 180)) + rect(l14 (-180 -730) (180 180)) + rect(l14 (-180 -4120) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l17 (-240 -790) (300 4790)) + rect(l17 (-151 -2501) (2 2)) + rect(l4 (-226 1049) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-851 -401) (2 2)) - rect(l6 (-651 859) (425 950)) + rect(l14 (410 1770) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l17 (-240 -1300) (300 1360)) + rect(l17 (-650 -2160) (1800 800)) + rect(l17 (-851 -401) (2 2)) + rect(l9 (-651 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2000 3500)) ) net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) + rect(l5 (725 2860) (250 1940)) + rect(l5 (-525 -1850) (300 300)) + rect(l5 (-25 1550) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l14 (-465 150) (180 180)) + rect(l17 (-91 -91) (2 2)) + rect(l17 (-151 -151) (300 300)) ) net(6 name(SUBSTRATE)) @@ -362,162 +364,162 @@ layout( # Nets with their geometries net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-2550 1800) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (4710 3010) (180 180)) + rect(l17 (-850 -240) (610 300)) + rect(l4 (-2550 1800) (425 1500)) + rect(l4 (950 -1500) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (6510 3010) (180 180)) + rect(l17 (-1140 -240) (900 300)) + rect(l4 (-1275 1800) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(3 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (8310 3010) (180 180)) + rect(l17 (-1140 -240) (900 300)) + rect(l4 (-1275 1800) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(4 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (10110 3010) (180 180)) + rect(l17 (-1140 -240) (900 300)) + rect(l4 (-1275 1800) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(5 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (11910 3010) (180 180)) + rect(l17 (-1140 -240) (900 300)) + rect(l4 (-1275 1800) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(6 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (13710 3010) (180 180)) + rect(l17 (-1140 -240) (900 300)) + rect(l4 (-1275 1800) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(7 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (15510 3010) (180 180)) + rect(l17 (-1140 -240) (900 300)) + rect(l4 (-1275 1800) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(8 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (17310 3010) (180 180)) + rect(l17 (-1140 -240) (900 300)) + rect(l4 (-1275 1800) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(9 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (19110 3010) (180 180)) + rect(l17 (-1140 -240) (900 300)) + rect(l4 (-1275 1800) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(10 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (20910 3010) (180 180)) + rect(l17 (-1140 -240) (900 300)) + rect(l4 (-1275 1800) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(11 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) - rect(l11 (-19530 590) (320 320)) - rect(l11 (17820 -320) (320 320)) - rect(l12 (-18400 -260) (200 200)) - rect(l12 (17940 -200) (200 200)) - rect(l13 (-18040 -300) (17740 400)) - rect(l13 (-17921 -201) (2 2)) - rect(l13 (-221 -201) (400 400)) - rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (22710 3010) (180 180)) + rect(l14 (-19700 720) (180 180)) + rect(l17 (18380 -1140) (900 300)) + rect(l17 (-19530 590) (320 320)) + rect(l17 (17820 -320) (320 320)) + rect(l18 (-18400 -260) (200 200)) + rect(l18 (17940 -200) (200 200)) + rect(l19 (-18040 -300) (17740 400)) + rect(l19 (-17921 -201) (2 2)) + rect(l19 (-221 -201) (400 400)) + rect(l19 (17740 -400) (400 400)) + rect(l4 (-245 850) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) rect(l3 (-1900 -3500) (600 3500)) rect(l3 (23300 -3500) (1400 3500)) rect(l3 (-100 -3500) (600 3500)) - rect(l8 (-24690 -1240) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l11 (-21741 859) (2 2)) - rect(l11 (-2351 -451) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23400 -800) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l2 (-23025 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l9 (-21975 -450) (500 1500)) - rect(l9 (22900 -1500) (500 1500)) + rect(l14 (-24690 -1240) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l14 (-180 -1280) (180 180)) + rect(l14 (23220 370) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l14 (-180 -1280) (180 180)) + rect(l17 (-21741 859) (2 2)) + rect(l17 (-2351 -451) (1200 800)) + rect(l17 (-750 -1450) (300 1400)) + rect(l17 (-101 -351) (2 2)) + rect(l17 (-1251 -401) (600 800)) + rect(l17 (23400 -800) (1200 800)) + rect(l17 (-750 -1450) (300 1400)) + rect(l17 (-101 -351) (2 2)) + rect(l17 (549 -401) (600 800)) + rect(l4 (-23025 -2550) (425 1500)) + rect(l4 (-400 -1500) (425 1500)) + rect(l4 (1275 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l15 (-21975 -450) (500 1500)) + rect(l15 (22900 -1500) (500 1500)) ) net(13 name(OUT) - rect(l11 (23440 3840) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l17 (23440 3840) (320 320)) + rect(l18 (-260 -260) (200 200)) + rect(l19 (-101 -101) (2 2)) + rect(l19 (-201 -201) (400 400)) + rect(l4 (-625 850) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(14 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) + rect(l14 (2510 3010) (180 180)) + rect(l17 (-250 -250) (320 320)) + rect(l18 (-260 -260) (200 200)) + rect(l19 (-101 -101) (2 2)) + rect(l19 (-201 -201) (400 400)) ) net(15 name(VSS) - rect(l8 (1110 1610) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-21741 -391) (2 2)) - rect(l11 (-1901 -401) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23850 -750) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l6 (-23700 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l10 (-21975 -2210) (500 1500)) - rect(l10 (22900 -1500) (500 1500)) + rect(l14 (1110 1610) (180 180)) + rect(l14 (-180 -1280) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l14 (23220 370) (180 180)) + rect(l14 (-180 -1280) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l17 (-21741 -391) (2 2)) + rect(l17 (-1901 -401) (300 1400)) + rect(l17 (-750 -1450) (1200 800)) + rect(l17 (-551 -401) (2 2)) + rect(l17 (-1251 -401) (600 800)) + rect(l17 (23850 -750) (300 1400)) + rect(l17 (-750 -1450) (1200 800)) + rect(l17 (-551 -401) (2 2)) + rect(l17 (549 -401) (600 800)) + rect(l9 (-23700 460) (425 950)) + rect(l9 (1975 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l16 (-21975 -2210) (500 1500)) + rect(l16 (22900 -1500) (500 1500)) ) # Outgoing pins and their connections to nets diff --git a/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 b/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 index 7ea0be0cd..2d7583393 100644 --- a/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 +++ b/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 @@ -10,49 +10,51 @@ layout( # Mask layers layer(l3 '1/0') - layer(l4 '5/0') - layer(l8 '8/0') - layer(l11 '9/0') - layer(l12 '10/0') - layer(l13 '11/0') - layer(l7) - layer(l2) + layer(l5 '5/0') + layer(l14 '8/0') + layer(l17 '9/0') + layer(l18 '10/0') + layer(l19 '11/0') + layer(l8) + layer(l4) + layer(l15) layer(l9) - layer(l6) - layer(l10) + layer(l16) # Mask layer connectivity - connect(l3 l3 l9) - connect(l4 l4 l8) - connect(l8 l4 l8 l11 l2 l9 l6 l10) - connect(l11 l8 l11 l12) - connect(l12 l11 l12 l13) - connect(l13 l12 l13) - connect(l7 l7) - connect(l2 l8 l2) - connect(l9 l3 l8 l9) - connect(l6 l8 l6) - connect(l10 l8 l10) + connect(l3 l3 l15) + connect(l5 l5 l14) + connect(l14 l5 l14 l17 l4 l15 l9 l16) + connect(l17 l14 l17 l18) + connect(l18 l17 l18 l19) + connect(l19 l18 l19) + connect(l8 l8) + connect(l4 l14 l4) + connect(l15 l3 l14 l15) + connect(l9 l14 l9) + connect(l16 l14 l16) # Global nets and connectivity - global(l7 SUBSTRATE) - global(l10 SUBSTRATE) + global(l8 SUBSTRATE) + global(l16 SUBSTRATE) # Device class section class(PM MOS4) class(NM MOS4) + class(PMHV MOS4) + class(NMHV MOS4) # Device abstracts section # Device abstracts list the pin shapes of the devices. device(D$PM PM terminal(S - rect(l2 (-550 -750) (425 1500)) + rect(l4 (-550 -750) (425 1500)) ) terminal(G - rect(l4 (-125 -750) (250 1500)) + rect(l5 (-125 -750) (250 1500)) ) terminal(D - rect(l2 (125 -750) (450 1500)) + rect(l4 (125 -750) (450 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -60,13 +62,13 @@ layout( ) device(D$PM$1 PM terminal(S - rect(l2 (-575 -750) (450 1500)) + rect(l4 (-575 -750) (450 1500)) ) terminal(G - rect(l4 (-125 -750) (250 1500)) + rect(l5 (-125 -750) (250 1500)) ) terminal(D - rect(l2 (125 -750) (425 1500)) + rect(l4 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -74,13 +76,13 @@ layout( ) device(D$PM$2 PM terminal(S - rect(l2 (-550 -750) (425 1500)) + rect(l4 (-550 -750) (425 1500)) ) terminal(G - rect(l4 (-125 -750) (250 1500)) + rect(l5 (-125 -750) (250 1500)) ) terminal(D - rect(l2 (125 -750) (425 1500)) + rect(l4 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -88,44 +90,44 @@ layout( ) device(D$NM NM terminal(S - rect(l6 (-550 -475) (425 950)) + rect(l9 (-550 -475) (425 950)) ) terminal(G - rect(l4 (-125 -475) (250 950)) + rect(l5 (-125 -475) (250 950)) ) terminal(D - rect(l6 (125 -475) (450 950)) + rect(l9 (125 -475) (450 950)) ) terminal(B - rect(l7 (-125 -475) (250 950)) + rect(l8 (-125 -475) (250 950)) ) ) device(D$NM$1 NM terminal(S - rect(l6 (-575 -475) (450 950)) + rect(l9 (-575 -475) (450 950)) ) terminal(G - rect(l4 (-125 -475) (250 950)) + rect(l5 (-125 -475) (250 950)) ) terminal(D - rect(l6 (125 -475) (425 950)) + rect(l9 (125 -475) (425 950)) ) terminal(B - rect(l7 (-125 -475) (250 950)) + rect(l8 (-125 -475) (250 950)) ) ) device(D$NM$2 NM terminal(S - rect(l6 (-550 -475) (425 950)) + rect(l9 (-550 -475) (425 950)) ) terminal(G - rect(l4 (-125 -475) (250 950)) + rect(l5 (-125 -475) (250 950)) ) terminal(D - rect(l6 (125 -475) (425 950)) + rect(l9 (125 -475) (425 950)) ) terminal(B - rect(l7 (-125 -475) (250 950)) + rect(l8 (-125 -475) (250 950)) ) ) @@ -138,70 +140,70 @@ layout( # Nets with their geometries net(1 name(VDD) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -790) (300 1700)) - rect(l11 (-1350 0) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l2 (-276 -2151) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) + rect(l14 (1110 5160) (180 180)) + rect(l14 (-180 920) (180 180)) + rect(l14 (-180 -730) (180 180)) + rect(l17 (-240 -790) (300 1700)) + rect(l17 (-1350 0) (2400 800)) + rect(l17 (-1151 -401) (2 2)) + rect(l4 (-276 -2151) (425 1500)) + rect(l4 (-400 -1500) (425 1500)) ) net(2 name(OUT) - rect(l8 (1810 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-1580 3760) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l11 (-110 1390) (300 1400)) - polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l11 (-141 -501) (2 2)) - rect(l11 (-1751 1099) (300 1400)) - rect(l11 (1100 -1700) (300 300)) - rect(l11 (-300 0) (300 1400)) - rect(l2 (-375 -1450) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) + rect(l14 (1810 1770) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l14 (-1580 3760) (180 180)) + rect(l14 (-180 -730) (180 180)) + rect(l14 (-180 -730) (180 180)) + rect(l14 (1220 920) (180 180)) + rect(l14 (-180 -1280) (180 180)) + rect(l14 (-180 370) (180 180)) + polygon(l17 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l17 (-110 1390) (300 1400)) + polygon(l17 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l17 (-141 -501) (2 2)) + rect(l17 (-1751 1099) (300 1400)) + rect(l17 (1100 -1700) (300 300)) + rect(l17 (-300 0) (300 1400)) + rect(l4 (-375 -1450) (425 1500)) + rect(l4 (-1800 -1500) (425 1500)) + rect(l9 (950 -4890) (425 950)) ) net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l6 (-951 859) (425 950)) + rect(l14 (410 1770) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l17 (-240 -1300) (300 1360)) + rect(l17 (-650 -2160) (2400 800)) + rect(l17 (-1151 -401) (2 2)) + rect(l9 (-951 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2600 3500)) ) net(5 name(B) - rect(l4 (1425 2860) (250 1940)) - rect(l4 (-345 -950) (300 300)) - rect(l4 (-205 650) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-285 1050) (180 180)) - rect(l11 (-71 -91) (2 2)) - rect(l11 (-171 -151) (300 300)) + rect(l5 (1425 2860) (250 1940)) + rect(l5 (-345 -950) (300 300)) + rect(l5 (-205 650) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l14 (-285 1050) (180 180)) + rect(l17 (-71 -91) (2 2)) + rect(l17 (-171 -151) (300 300)) ) net(6 name(A) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-325 -1850) (300 300)) - rect(l4 (-225 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-265 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) + rect(l5 (725 2860) (250 1940)) + rect(l5 (-325 -1850) (300 300)) + rect(l5 (-225 1550) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l14 (-265 150) (180 180)) + rect(l17 (-91 -91) (2 2)) + rect(l17 (-151 -151) (300 300)) ) net(7 name(SUBSTRATE)) net(8 - rect(l6 (975 1660) (425 950)) - rect(l6 (-400 -950) (425 950)) + rect(l9 (975 1660) (425 950)) + rect(l9 (-400 -950) (425 950)) ) # Outgoing pins and their connections to nets @@ -275,46 +277,46 @@ layout( # Nets with their geometries net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (299 399) (2 2)) - rect(l2 (-651 -2151) (425 1500)) + rect(l14 (410 6260) (180 180)) + rect(l14 (-180 -730) (180 180)) + rect(l14 (-180 -730) (180 180)) + rect(l17 (-240 -240) (300 1400)) + rect(l17 (-650 300) (1800 800)) + rect(l17 (-1450 -1100) (300 300)) + rect(l17 (299 399) (2 2)) + rect(l4 (-651 -2151) (425 1500)) ) net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (1110 5160) (180 180)) + rect(l14 (-180 920) (180 180)) + rect(l14 (-180 -730) (180 180)) + rect(l14 (-180 -4120) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l17 (-240 -790) (300 4790)) + rect(l17 (-151 -2501) (2 2)) + rect(l4 (-226 1049) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-851 -401) (2 2)) - rect(l6 (-651 859) (425 950)) + rect(l14 (410 1770) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l17 (-240 -1300) (300 1360)) + rect(l17 (-650 -2160) (1800 800)) + rect(l17 (-851 -401) (2 2)) + rect(l9 (-651 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2000 3500)) ) net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) + rect(l5 (725 2860) (250 1940)) + rect(l5 (-525 -1850) (300 300)) + rect(l5 (-25 1550) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l14 (-465 150) (180 180)) + rect(l17 (-91 -91) (2 2)) + rect(l17 (-151 -151) (300 300)) ) net(6 name(SUBSTRATE)) @@ -362,162 +364,162 @@ layout( # Nets with their geometries net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-1175 1800) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) + rect(l14 (4710 3010) (180 180)) + rect(l17 (-850 -240) (610 300)) + rect(l4 (-1175 1800) (425 1500)) + rect(l4 (-1800 -1500) (425 1500)) + rect(l9 (950 -4890) (425 950)) ) net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (6510 3010) (180 180)) + rect(l17 (-1140 -240) (900 300)) + rect(l4 (-1275 1800) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(3 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (8310 3010) (180 180)) + rect(l17 (-1140 -240) (900 300)) + rect(l4 (-1275 1800) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(4 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (10110 3010) (180 180)) + rect(l17 (-1140 -240) (900 300)) + rect(l4 (-1275 1800) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(5 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (11910 3010) (180 180)) + rect(l17 (-1140 -240) (900 300)) + rect(l4 (-1275 1800) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(6 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (13710 3010) (180 180)) + rect(l17 (-1140 -240) (900 300)) + rect(l4 (-1275 1800) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(7 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (15510 3010) (180 180)) + rect(l17 (-1140 -240) (900 300)) + rect(l4 (-1275 1800) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(8 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (17310 3010) (180 180)) + rect(l17 (-1140 -240) (900 300)) + rect(l4 (-1275 1800) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(9 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (19110 3010) (180 180)) + rect(l17 (-1140 -240) (900 300)) + rect(l4 (-1275 1800) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(10 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (20910 3010) (180 180)) + rect(l17 (-1140 -240) (900 300)) + rect(l4 (-1275 1800) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(11 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) - rect(l11 (-19530 590) (320 320)) - rect(l11 (17820 -320) (320 320)) - rect(l12 (-18400 -260) (200 200)) - rect(l12 (17940 -200) (200 200)) - rect(l13 (-18040 -300) (17740 400)) - rect(l13 (-17921 -201) (2 2)) - rect(l13 (-221 -201) (400 400)) - rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l14 (22710 3010) (180 180)) + rect(l14 (-19700 720) (180 180)) + rect(l17 (18380 -1140) (900 300)) + rect(l17 (-19530 590) (320 320)) + rect(l17 (17820 -320) (320 320)) + rect(l18 (-18400 -260) (200 200)) + rect(l18 (17940 -200) (200 200)) + rect(l19 (-18040 -300) (17740 400)) + rect(l19 (-17921 -201) (2 2)) + rect(l19 (-221 -201) (400 400)) + rect(l19 (17740 -400) (400 400)) + rect(l4 (-245 850) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) rect(l3 (-1900 -3500) (600 3500)) rect(l3 (23300 -3500) (1400 3500)) rect(l3 (-100 -3500) (600 3500)) - rect(l8 (-24690 -1240) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l11 (-21741 859) (2 2)) - rect(l11 (-2351 -451) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23400 -800) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l2 (-23025 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l9 (-21975 -450) (500 1500)) - rect(l9 (22900 -1500) (500 1500)) + rect(l14 (-24690 -1240) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l14 (-180 -1280) (180 180)) + rect(l14 (23220 370) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l14 (-180 -1280) (180 180)) + rect(l17 (-21741 859) (2 2)) + rect(l17 (-2351 -451) (1200 800)) + rect(l17 (-750 -1450) (300 1400)) + rect(l17 (-101 -351) (2 2)) + rect(l17 (-1251 -401) (600 800)) + rect(l17 (23400 -800) (1200 800)) + rect(l17 (-750 -1450) (300 1400)) + rect(l17 (-101 -351) (2 2)) + rect(l17 (549 -401) (600 800)) + rect(l4 (-23025 -2550) (425 1500)) + rect(l4 (-400 -1500) (425 1500)) + rect(l4 (1275 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l4 (1375 -1500) (425 1500)) + rect(l15 (-21975 -450) (500 1500)) + rect(l15 (22900 -1500) (500 1500)) ) net(13 name(OUT) - rect(l11 (23440 3840) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l17 (23440 3840) (320 320)) + rect(l18 (-260 -260) (200 200)) + rect(l19 (-101 -101) (2 2)) + rect(l19 (-201 -201) (400 400)) + rect(l4 (-625 850) (425 1500)) + rect(l9 (-425 -4890) (425 950)) ) net(14 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) + rect(l14 (2510 3010) (180 180)) + rect(l17 (-250 -250) (320 320)) + rect(l18 (-260 -260) (200 200)) + rect(l19 (-101 -101) (2 2)) + rect(l19 (-201 -201) (400 400)) ) net(15 name(VSS) - rect(l8 (1110 1610) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-21741 -391) (2 2)) - rect(l11 (-1901 -401) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23850 -750) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l6 (-23700 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l10 (-21975 -2210) (500 1500)) - rect(l10 (22900 -1500) (500 1500)) + rect(l14 (1110 1610) (180 180)) + rect(l14 (-180 -1280) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l14 (23220 370) (180 180)) + rect(l14 (-180 -1280) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l17 (-21741 -391) (2 2)) + rect(l17 (-1901 -401) (300 1400)) + rect(l17 (-750 -1450) (1200 800)) + rect(l17 (-551 -401) (2 2)) + rect(l17 (-1251 -401) (600 800)) + rect(l17 (23850 -750) (300 1400)) + rect(l17 (-750 -1450) (1200 800)) + rect(l17 (-551 -401) (2 2)) + rect(l17 (549 -401) (600 800)) + rect(l9 (-23700 460) (425 950)) + rect(l9 (1975 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l9 (1375 -950) (425 950)) + rect(l16 (-21975 -2210) (500 1500)) + rect(l16 (22900 -1500) (500 1500)) ) # Outgoing pins and their connections to nets diff --git a/testdata/lvs/ringo_xdevice.cir b/testdata/lvs/ringo_xdevice.cir new file mode 100644 index 000000000..b3129f54e --- /dev/null +++ b/testdata/lvs/ringo_xdevice.cir @@ -0,0 +1,35 @@ + +.SUBCKT XPMOS S G D B PARAMS: L=1U W=1U + M$1 S G D B PMOS L=L W=W +.ENDS PMOS + +.SUBCKT NMOS S G D B PARAMS: L=1U W=1U + M$1 S G D B NMOS L=L W=W +.ENDS NMOS + +.SUBCKT RINGO VSS VDD FB ENABLE OUT +X$1 VDD 1 VSS VDD FB ENABLE VSS ND2X1 +X$2 VDD 2 VSS VDD 1 VSS INVX1 +X$3 VDD 3 VSS VDD 2 VSS INVX1 +X$4 VDD 4 VSS VDD 3 VSS INVX1 +X$5 VDD 5 VSS VDD 4 VSS INVX1 +X$6 VDD 6 VSS VDD 5 VSS INVX1 +X$7 VDD 7 VSS VDD 6 VSS INVX1 +X$8 VDD 8 VSS VDD 7 VSS INVX1 +X$9 VDD 9 VSS VDD 8 VSS INVX1 +X$10 VDD 10 VSS VDD 9 VSS INVX1 +X$11 VDD FB VSS VDD 10 VSS INVX1 +X$12 VDD OUT VSS VDD FB VSS INVX1 +.ENDS RINGO + +.SUBCKT ND2X1 VDD OUT VSS NWELL B A BULK +X$1 OUT A VDD NWELL XPMOS L=0.25U W=1.5U +X$2 VDD B OUT NWELL XPMOS L=0.25U W=1.5U +X$3 VSS A 1 BULK NMOS L=0.25U W=0.95U +X$4 1 B OUT BULK NMOS L=0.25U W=0.95U +.ENDS ND2X1 + +.SUBCKT INVX1 VDD OUT VSS NWELL IN BULK +X$1 VDD IN OUT NWELL XPMOS L=0.25U W=1.5U +X$2 VSS IN OUT BULK NMOS L=0.25U W=0.95U +.ENDS INVX1 diff --git a/testdata/python/dbLayoutToNetlist.py b/testdata/python/dbLayoutToNetlist.py index ea7df5f46..11e395309 100644 --- a/testdata/python/dbLayoutToNetlist.py +++ b/testdata/python/dbLayoutToNetlist.py @@ -416,13 +416,13 @@ end; self.assertEqual(str(l2n.netlist()), """circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS); subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I7,$6=OSC,$7=VDD); - subcircuit INV2PAIR $2 (BULK=VSS,$2=(null),$3=VDD,$4=VSS,$5=FB,$6=$I13,$7=VDD); - subcircuit INV2PAIR $3 (BULK=VSS,$2=(null),$3=VDD,$4=VSS,$5=$I13,$6=$I5,$7=VDD); - subcircuit INV2PAIR $4 (BULK=VSS,$2=(null),$3=VDD,$4=VSS,$5=$I5,$6=$I6,$7=VDD); - subcircuit INV2PAIR $5 (BULK=VSS,$2=(null),$3=VDD,$4=VSS,$5=$I6,$6=$I7,$7=VDD); + subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I13,$7=VDD); + subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I13,$6=$I5,$7=VDD); + subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I5,$6=$I6,$7=VDD); + subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I6,$6=$I7,$7=VDD); end; circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1); - subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=(null),OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK); + subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK); subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK); end; circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK); diff --git a/testdata/ruby/dbLayoutToNetlist.rb b/testdata/ruby/dbLayoutToNetlist.rb index 325e6284d..727ab064a 100644 --- a/testdata/ruby/dbLayoutToNetlist.rb +++ b/testdata/ruby/dbLayoutToNetlist.rb @@ -455,13 +455,13 @@ END assert_equal(l2n.netlist.to_s, < 6, "B" => 7.0) + assert_equal(g, "rba_test_recipe: A=#6,B=##7") + assert_equal("%g" % RBA::Recipe::make(g).to_s, "42") + assert_equal("%g" % RBA::Recipe::make(g, "C" => 1.5).to_s, "63") + + my_recipe._destroy + my_recipe = nil + GC.start + + end + end load("test_epilogue.rb")