diff --git a/src/db/db/dbNetlistCompare.cc b/src/db/db/dbNetlistCompare.cc
index 46063082f..d21c4388b 100644
--- a/src/db/db/dbNetlistCompare.cc
+++ b/src/db/db/dbNetlistCompare.cc
@@ -736,7 +736,6 @@ public:
 
       size_t pin_id = i->pin ()->id ();
       const db::Circuit *cr = sc->circuit_ref ();
-      const db::Net *net_at_pin = cr->net_for_pin (pin_id);
 
       std::map<const db::Circuit *, CircuitMapper>::const_iterator icm = circuit_map->find (cr);
       if (icm == circuit_map->end ()) {
@@ -756,85 +755,24 @@ public:
       //  NOTE: if cm is given, cr and pin_id are given in terms of the canonical "other" circuit.
       //  For c1 this is the c1->c2 mapper, for c2 this is the c2->c2 dummy mapper.
 
-      cr = cm->other ();
       pin_id = cm->other_pin_from_this_pin (pin_id);
 
       //  realize pin swapping by normalization of pin ID
 
-      pin_id = pin_map->normalize_pin_id (cr, pin_id);
+      pin_id = pin_map->normalize_pin_id (cm->other (), pin_id);
 
-      //  shortcut for idle pin (e.g. when abstract circuits are addressed: just include a transition to 0
-      //  to make the net distinguishable from a net without this connection.
+      //  Subcircuits are routed to a null node and descend from a virtual node inside the subcircuit.
+      //  The reasoning is that this way we don't need #pins*(#pins-1) edges but rather #pins.
 
-      if (! net_at_pin || net_at_pin->is_floating ()) {   //  @@@ use this always
-
-        Transition ed (sc, circuit_cat, pin_id, pin_id);
-
-        std::map<const void *, size_t>::const_iterator in = n2entry.find ((const void *) sc);
-        if (in == n2entry.end ()) {
-          in = n2entry.insert (std::make_pair ((const void *) sc, m_edges.size ())).first;
-          m_edges.push_back (std::make_pair (std::vector<Transition> (), std::make_pair (size_t (0), (const db::Net *) 0)));
-        }
-
-        m_edges [in->second].first.push_back (ed);
-
-        continue;
+      Transition ed (sc, circuit_cat, pin_id, pin_id);
 
+      std::map<const void *, size_t>::const_iterator in = n2entry.find ((const void *) sc);
+      if (in == n2entry.end ()) {
+        in = n2entry.insert (std::make_pair ((const void *) sc, m_edges.size ())).first;
+        m_edges.push_back (std::make_pair (std::vector<Transition> (), std::make_pair (size_t (0), (const db::Net *) 0)));
       }
 
-      //  @@@ drop this stupid logic:
-
-      //  we cannot afford creating edges from all to all other pins, so we just create edges to the previous and next
-      //  pin. This may take more iterations to solve, but should be equivalent.
-
-      size_t pin_count = cr->pin_count ();
-
-      //  take a number if additional pins as edges: this allows identifying a pin as dependent
-      //  from other pins hence nets are propagated. We assume that there are 4 power pins max so
-      //  5 additional pins should be sufficient to capture one additional non-power pin.
-
-      size_t take_additional_pins = 5;
-
-      std::vector<size_t> pids;
-      pids.reserve (take_additional_pins + 1);
-
-      for (size_t n = 0; n < take_additional_pins; ++n) {
-        size_t add_pin_id = (pin_id + n + 1) % pin_count;
-        if (add_pin_id == pin_id) {
-          break;
-        }
-        if (cm->has_this_pin_for_other_pin (add_pin_id)
-             //  NOTE: we do not include transitions to equivalent pins in our graph intentionally.
-             //  Reasoning: for abstract circuits, transitions are basically useless. For more than
-             //  two equivalent pins, the transitions are unpredictable.
-             && pin_map->normalize_pin_id (cr, add_pin_id) != pin_id) {
-          pids.push_back (add_pin_id);
-        } else {
-          //  skip pins without mapping
-          ++take_additional_pins;
-        }
-      }
-
-      for (std::vector<size_t>::const_iterator i = pids.begin (); i != pids.end (); ++i) {
-
-        size_t pin2_id = *i;
-        size_t this_pin2_id = cm->this_pin_from_other_pin (pin2_id);
-
-        //  NOTE: if a pin mapping is given, EdgeDesc::pin1_id and EdgeDesc::pin2_id are given
-        //  as pin ID's of the other circuit.
-        Transition ed (sc, circuit_cat, pin_id, pin_map->normalize_pin_id (cr, pin2_id));
-
-        const db::Net *net2 = sc->net_for_pin (this_pin2_id);
-
-        std::map<const void *, size_t>::const_iterator in = n2entry.find ((const void *) net2);
-        if (in == n2entry.end ()) {
-          in = n2entry.insert (std::make_pair ((const void *) net2, m_edges.size ())).first;
-          m_edges.push_back (std::make_pair (std::vector<Transition> (), std::make_pair (size_t (0), net2)));
-        }
-
-        m_edges [in->second].first.push_back (ed);
-
-      }
+      m_edges [in->second].first.push_back (ed);
 
     }
 
@@ -884,17 +822,13 @@ public:
     std::map<const db::Net *, size_t> n2entry;
 
     size_t circuit_cat = circuit_categorizer.cat_for_subcircuit (sc);
-    if (! circuit_cat) {
-      tl_assert (false); // @@@@
-    }
+    tl_assert (circuit_cat != 0);
 
     const db::Circuit *cr = sc->circuit_ref ();
     tl_assert (cr != 0);
 
     std::map<const db::Circuit *, CircuitMapper>::const_iterator icm = circuit_map->find (cr);
-    if (icm == circuit_map->end ()) {
-      tl_assert (false); // @@@@
-    }
+    tl_assert (icm != circuit_map->end ());
 
     const CircuitMapper *cm = & icm->second;
 
@@ -1430,7 +1364,20 @@ NetGraph::build (const db::Circuit *c, DeviceCategorizer &device_categorizer, Ci
   //  create subcircuit distribution nodes
 
   for (db::Circuit::const_subcircuit_iterator i = c->begin_subcircuits (); i != c->end_subcircuits (); ++i) {
+
+    size_t circuit_cat = circuit_categorizer.cat_for_subcircuit (i.operator-> ());
+    if (! circuit_cat) {
+      continue;
+    }
+
+    const db::Circuit *cr = i->circuit_ref ();
+    std::map<const db::Circuit *, CircuitMapper>::const_iterator icm = circuit_and_pin_mapping->find (cr);
+    if (icm == circuit_and_pin_mapping->end ()) {
+      continue;
+    }
+
     m_distro_nodes.insert (std::make_pair (i.operator-> (), NetGraphNode (i.operator-> (), circuit_categorizer, circuit_and_pin_mapping, circuit_pin_mapper)));
+
   }
 
   for (std::map<const db::SubCircuit *, NetGraphNode>::iterator i = m_distro_nodes.begin (); i != m_distro_nodes.end (); ++i) {
@@ -1541,6 +1488,30 @@ NetGraph::derive_node_identities_for_edges (NetGraphNode::edge_iterator e, NetGr
   return new_nodes;
 }
 
+const db::SubCircuit *subcircuit_on_edges (NetGraphNode::edge_iterator e, NetGraphNode::edge_iterator ee, CompareData *data)
+{
+  const db::SubCircuit *subcircuit_on_node = 0;
+  bool subcircuit_on_node_ambiguous = false;
+
+  while (e != ee) {
+    for (std::vector<NetGraphNode::Transition>::const_iterator t = e->first.begin (); t != e->first.end (); ++t) {
+      if (t->is_for_subcircuit ()) {
+        const db::SubCircuit *sc = t->subcircuit_pair ().first;
+        if (data->subcircuit_categorizer->has_cat_for (sc)) {
+          //  ignore known subcircuits
+        } else if (! subcircuit_on_node || subcircuit_on_node == sc) {
+          subcircuit_on_node = sc;
+        } else {
+          subcircuit_on_node_ambiguous = true;
+        }
+      }
+    }
+    ++e;
+  }
+
+  return subcircuit_on_node_ambiguous ? 0 : subcircuit_on_node;
+}
+
 size_t
 NetGraph::derive_node_identities (size_t net_index, size_t depth, size_t n_branch, TentativeNodeMapping *tentative, bool with_ambiguous, CompareData *data)
 {
@@ -1563,21 +1534,7 @@ NetGraph::derive_node_identities (size_t net_index, size_t depth, size_t n_branc
   for (NetGraphNode::edge_iterator e = n->begin (); e != n->end (); ) {
 
     NetGraphNode::edge_iterator ee = e;
-
-    const db::SubCircuit *subcircuit_on_node = 0;
-    bool subcircuit_on_node_ambiguous = false;
-
     while (ee != n->end () && ee->first == e->first) {
-      if (ee->first.size () == 1 /*@@@ needed?*/ && ee->first.front ().is_for_subcircuit ()) {
-        const db::SubCircuit *sc = ee->first.front ().subcircuit_pair ().first;
-        if (data->subcircuit_categorizer->has_cat_for (sc)) {
-          //  ignore known subcircuits
-        } else if (! subcircuit_on_node || subcircuit_on_node == sc) {
-          subcircuit_on_node = sc;
-        } else {
-          subcircuit_on_node_ambiguous = true;
-        }
-      }
       ++ee;
     }
 
@@ -1588,29 +1545,17 @@ NetGraph::derive_node_identities (size_t net_index, size_t depth, size_t n_branc
     //  providing the other endpoints and nil at our side. This saves us creating #pin*(#pin-1) edges
     //  per circuit. This happens through a dummy node ("distro_node").
 
-    if (subcircuit_on_node && ! subcircuit_on_node_ambiguous) {
+    const db::SubCircuit *subcircuit_on_node = subcircuit_on_edges (e, ee, data);
+    if (subcircuit_on_node) {
 
       NetGraphNode::edge_iterator e_other = nother->find_edge (e->first);
       NetGraphNode::edge_iterator ee_other = e_other;
-
-      const db::SubCircuit *other_subcircuit_on_node = 0;
-      bool other_subcircuit_on_node_ambiguous = false;
-
       while (ee_other != nother->end () && ee_other->first == e_other->first) {
-        if (ee_other->first.size () == 1 /*@@@ needed?*/ && ee_other->first.front ().is_for_subcircuit ()) {
-          const db::SubCircuit *sc = ee_other->first.front ().subcircuit_pair ().first;
-          if (data->subcircuit_categorizer->has_cat_for (sc)) {
-            //  ignore known subcircuits
-          } else if (! other_subcircuit_on_node || other_subcircuit_on_node == sc) {
-            other_subcircuit_on_node = sc;
-          } else {
-            other_subcircuit_on_node_ambiguous = true;
-          }
-        }
         ++ee_other;
       }
 
-      if (other_subcircuit_on_node && ! other_subcircuit_on_node_ambiguous) {
+      const db::SubCircuit *other_subcircuit_on_node = subcircuit_on_edges (e_other, ee_other, data);
+      if (other_subcircuit_on_node) {
 
         NetGraphNode &dn = distro_node (subcircuit_on_node);
         NetGraphNode &dn_other = data->other->distro_node (other_subcircuit_on_node);
diff --git a/testdata/lvs/ringo_simple_blackboxing.cir b/testdata/lvs/ringo_simple_blackboxing.cir
index c24088217..e6a7e5bcc 100644
--- a/testdata/lvs/ringo_simple_blackboxing.cir
+++ b/testdata/lvs/ringo_simple_blackboxing.cir
@@ -44,17 +44,8 @@ X$21 6 11 9 6 15 9 INVX1
 * pin OUT
 * pin VSS
 * pin 
-* pin SUBSTRATE
+* pin BULK
 .SUBCKT INVX2 1 2 3 4 5 6
-* net 1 IN
-* net 2 VDD
-* net 3 OUT
-* net 4 VSS
-* net 6 SUBSTRATE
-* device instance $1 r0 *1 0.85,5.8 PMOS
-M$1 2 1 3 5 PMOS L=0.25U W=3U AS=0.975P AD=0.975P PS=5.8U PD=5.8U
-* device instance $3 r0 *1 0.85,2.135 NMOS
-M$3 4 1 3 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U
 .ENDS INVX2
 
 * cell INVX1
@@ -63,17 +54,8 @@ M$3 4 1 3 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U
 * pin VSS
 * pin 
 * pin IN
-* pin SUBSTRATE
+* pin BULK
 .SUBCKT INVX1 1 2 3 4 5 6
-* net 1 VDD
-* net 2 OUT
-* net 3 VSS
-* net 5 IN
-* net 6 SUBSTRATE
-* device instance $1 r0 *1 0.85,5.8 PMOS
-M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
-* device instance $2 r0 *1 0.85,2.135 NMOS
-M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
 .ENDS INVX1
 
 * cell ND2X1
@@ -83,20 +65,6 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
 * pin 
 * pin B
 * pin A
-* pin SUBSTRATE
+* pin BULK
 .SUBCKT ND2X1 1 2 3 4 5 6 7
-* net 1 VDD
-* net 2 OUT
-* net 3 VSS
-* net 5 B
-* net 6 A
-* net 7 SUBSTRATE
-* device instance $1 r0 *1 0.85,5.8 PMOS
-M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
-* device instance $2 r0 *1 1.55,5.8 PMOS
-M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
-* device instance $3 r0 *1 0.85,2.135 NMOS
-M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
-* device instance $4 r0 *1 1.55,2.135 NMOS
-M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
 .ENDS ND2X1
diff --git a/testdata/lvs/ringo_simple_blackboxing.lvsdb b/testdata/lvs/ringo_simple_blackboxing.lvsdb
index e8e2e73f4..2a5a511ed 100644
--- a/testdata/lvs/ringo_simple_blackboxing.lvsdb
+++ b/testdata/lvs/ringo_simple_blackboxing.lvsdb
@@ -15,7 +15,7 @@ layout(
  layer(l11 '9/0')
  layer(l12 '10/0')
  layer(l13 '11/0')
- layer(l7)
+ layer(l7 '13/0')
  layer(l1)
  layer(l9)
  layer(l5)
@@ -42,459 +42,72 @@ layout(
  class(PMOS MOS4)
  class(NMOS MOS4)
 
- # Device abstracts section
- # Device abstracts list the pin shapes of the devices.
- device(D$PMOS PMOS
-  terminal(S
-   rect(l1 (-550 -750) (425 1500))
-  )
-  terminal(G
-   rect(l4 (-125 -750) (250 1500))
-  )
-  terminal(D
-   rect(l1 (125 -750) (450 1500))
-  )
-  terminal(B
-   rect(l3 (-125 -750) (250 1500))
-  )
- )
- device(D$PMOS$1 PMOS
-  terminal(S
-   rect(l1 (-575 -750) (450 1500))
-  )
-  terminal(G
-   rect(l4 (-125 -750) (250 1500))
-  )
-  terminal(D
-   rect(l1 (125 -750) (425 1500))
-  )
-  terminal(B
-   rect(l3 (-125 -750) (250 1500))
-  )
- )
- device(D$PMOS$2 PMOS
-  terminal(S
-   rect(l1 (-550 -750) (425 1500))
-  )
-  terminal(G
-   rect(l4 (-125 -750) (250 1500))
-  )
-  terminal(D
-   rect(l1 (125 -750) (425 1500))
-  )
-  terminal(B
-   rect(l3 (-125 -750) (250 1500))
-  )
- )
- device(D$NMOS NMOS
-  terminal(S
-   rect(l5 (-550 -475) (425 950))
-  )
-  terminal(G
-   rect(l4 (-125 -475) (250 950))
-  )
-  terminal(D
-   rect(l5 (125 -475) (450 950))
-  )
-  terminal(B
-   rect(l7 (-125 -475) (250 950))
-  )
- )
- device(D$NMOS$1 NMOS
-  terminal(S
-   rect(l5 (-575 -475) (450 950))
-  )
-  terminal(G
-   rect(l4 (-125 -475) (250 950))
-  )
-  terminal(D
-   rect(l5 (125 -475) (425 950))
-  )
-  terminal(B
-   rect(l7 (-125 -475) (250 950))
-  )
- )
- device(D$NMOS$2 NMOS
-  terminal(S
-   rect(l5 (-550 -475) (425 950))
-  )
-  terminal(G
-   rect(l4 (-125 -475) (250 950))
-  )
-  terminal(D
-   rect(l5 (125 -475) (425 950))
-  )
-  terminal(B
-   rect(l7 (-125 -475) (250 950))
-  )
- )
-
  # Circuit section
  # Circuits are the hierarchical building blocks of the netlist.
  circuit(ND2X1
 
-  # Nets with their geometries
-  net(1 name(VDD)
-   rect(l8 (1110 5160) (180 180))
-   rect(l8 (-180 920) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l11 (-240 -790) (300 1700))
-   rect(l11 (-1350 0) (2400 800))
-   rect(l11 (-1151 -401) (2 2))
-   rect(l1 (-276 -2151) (425 1500))
-   rect(l1 (-400 -1500) (425 1500))
-  )
-  net(2 name(OUT)
-   rect(l8 (1810 1770) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l8 (-1580 3760) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (1220 920) (180 180))
-   rect(l8 (-180 -1280) (180 180))
-   rect(l8 (-180 370) (180 180))
-   polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
-   rect(l11 (-110 1390) (300 1400))
-   polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
-   rect(l11 (-141 -501) (2 2))
-   rect(l11 (-1751 1099) (300 1400))
-   rect(l11 (1100 -1700) (300 300))
-   rect(l11 (-300 0) (300 1400))
-   rect(l1 (-1750 -1450) (425 1500))
-   rect(l1 (950 -1500) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
-  )
-  net(3 name(VSS)
-   rect(l8 (410 1770) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l11 (-240 -1300) (300 1360))
-   rect(l11 (-650 -2160) (2400 800))
-   rect(l11 (-1151 -401) (2 2))
-   rect(l5 (-951 859) (425 950))
-  )
-  net(4
-   rect(l3 (-100 4500) (2600 3500))
-  )
-  net(5 name(B)
-   rect(l4 (1425 2860) (250 1940))
-   rect(l4 (-345 -950) (300 300))
-   rect(l4 (-205 650) (250 2000))
-   rect(l4 (-250 -2000) (250 2000))
-   rect(l4 (-250 -5390) (250 1450))
-   rect(l8 (-285 1050) (180 180))
-   rect(l11 (-71 -91) (2 2))
-   rect(l11 (-171 -151) (300 300))
-  )
-  net(6 name(A)
-   rect(l4 (725 2860) (250 1940))
-   rect(l4 (-325 -1850) (300 300))
-   rect(l4 (-225 1550) (250 2000))
-   rect(l4 (-250 -2000) (250 2000))
-   rect(l4 (-250 -5390) (250 1450))
-   rect(l8 (-265 150) (180 180))
-   rect(l11 (-91 -91) (2 2))
-   rect(l11 (-151 -151) (300 300))
-  )
-  net(7 name(SUBSTRATE))
-  net(8
-   rect(l5 (975 1660) (425 950))
-   rect(l5 (-400 -950) (425 950))
-  )
+  # Circuit boundary
+  rect((-100 249) (2600 7751))
 
   # Outgoing pins and their connections to nets
-  pin(1 name(VDD))
-  pin(2 name(OUT))
-  pin(3 name(VSS))
-  pin(4)
-  pin(5 name(B))
-  pin(6 name(A))
-  pin(7 name(SUBSTRATE))
-
-  # Devices and their connections
-  device(1 D$PMOS
-   location(850 5800)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0.6375)
-   param(AD 0.3375)
-   param(PS 3.85)
-   param(PD 1.95)
-   terminal(S 2)
-   terminal(G 6)
-   terminal(D 1)
-   terminal(B 4)
-  )
-  device(2 D$PMOS$1
-   location(1550 5800)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0.3375)
-   param(AD 0.6375)
-   param(PS 1.95)
-   param(PD 3.85)
-   terminal(S 1)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(3 D$NMOS
-   location(850 2135)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0.40375)
-   param(AD 0.21375)
-   param(PS 2.75)
-   param(PD 1.4)
-   terminal(S 3)
-   terminal(G 6)
-   terminal(D 8)
-   terminal(B 7)
-  )
-  device(4 D$NMOS$1
-   location(1550 2135)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0.21375)
-   param(AD 0.40375)
-   param(PS 1.4)
-   param(PD 2.75)
-   terminal(S 8)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 7)
-  )
+  pin(name(VDD))
+  pin(name(OUT))
+  pin(name(VSS))
+  pin()
+  pin(name(B))
+  pin(name(A))
+  pin(name(BULK))
 
  )
  circuit(INVX1
 
-  # Nets with their geometries
-  net(1 name(VDD)
-   rect(l8 (410 6260) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l11 (-240 -240) (300 1400))
-   rect(l11 (-650 300) (1800 800))
-   rect(l11 (-1450 -1100) (300 300))
-   rect(l11 (299 399) (2 2))
-   rect(l1 (-651 -2151) (425 1500))
-  )
-  net(2 name(OUT)
-   rect(l8 (1110 5160) (180 180))
-   rect(l8 (-180 920) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (-180 -4120) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l11 (-240 -790) (300 4790))
-   rect(l11 (-151 -2501) (2 2))
-   rect(l1 (-226 1049) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
-  )
-  net(3 name(VSS)
-   rect(l8 (410 1770) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l11 (-240 -1300) (300 1360))
-   rect(l11 (-650 -2160) (1800 800))
-   rect(l11 (-851 -401) (2 2))
-   rect(l5 (-651 859) (425 950))
-  )
-  net(4
-   rect(l3 (-100 4500) (2000 3500))
-  )
-  net(5 name(IN)
-   rect(l4 (725 2860) (250 1940))
-   rect(l4 (-525 -1850) (300 300))
-   rect(l4 (-25 1550) (250 2000))
-   rect(l4 (-250 -2000) (250 2000))
-   rect(l4 (-250 -5390) (250 1450))
-   rect(l8 (-465 150) (180 180))
-   rect(l11 (-91 -91) (2 2))
-   rect(l11 (-151 -151) (300 300))
-  )
-  net(6 name(SUBSTRATE))
+  # Circuit boundary
+  rect((-100 249) (2000 7751))
 
   # Outgoing pins and their connections to nets
-  pin(1 name(VDD))
-  pin(2 name(OUT))
-  pin(3 name(VSS))
-  pin(4)
-  pin(5 name(IN))
-  pin(6 name(SUBSTRATE))
-
-  # Devices and their connections
-  device(1 D$PMOS$2
-   location(850 5800)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0.6375)
-   param(AD 0.6375)
-   param(PS 3.85)
-   param(PD 3.85)
-   terminal(S 1)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(2 D$NMOS$2
-   location(850 2135)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0.40375)
-   param(AD 0.40375)
-   param(PS 2.75)
-   param(PD 2.75)
-   terminal(S 3)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 6)
-  )
+  pin(name(VDD))
+  pin(name(OUT))
+  pin(name(VSS))
+  pin()
+  pin(name(IN))
+  pin(name(BULK))
 
  )
  circuit(INVX2
 
-  # Nets with their geometries
-  net(1 name(IN)
-   rect(l4 (725 2860) (250 1940))
-   rect(l4 (-225 -1300) (675 450))
-   rect(l4 (0 -1100) (250 1950))
-   rect(l4 (-1225 -1850) (300 300))
-   rect(l4 (675 1550) (250 2000))
-   rect(l4 (-250 -2000) (250 2000))
-   rect(l4 (-950 -2000) (250 2000))
-   rect(l4 (-250 -2000) (250 2000))
-   rect(l4 (450 -5390) (250 1450))
-   rect(l4 (-950 -1450) (250 1450))
-   rect(l8 (-465 150) (180 180))
-   rect(l11 (-91 -91) (2 2))
-   rect(l11 (-151 -151) (300 300))
-  )
-  net(2 name(VDD)
-   rect(l8 (410 6260) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (1220 920) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l11 (-1640 -240) (300 1400))
-   rect(l11 (-650 300) (2400 800))
-   rect(l11 (-2050 -1100) (300 300))
-   rect(l11 (1100 -300) (300 300))
-   rect(l11 (-1101 399) (2 2))
-   rect(l11 (799 -2101) (300 1400))
-   rect(l1 (-1750 -1450) (425 1500))
-   rect(l1 (950 -1500) (425 1500))
-  )
-  net(3 name(OUT)
-   rect(l8 (1110 5160) (180 180))
-   rect(l8 (-180 920) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (-180 -4120) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l11 (-240 -790) (300 4790))
-   rect(l11 (-151 -2501) (2 2))
-   rect(l1 (-226 1049) (425 1500))
-   rect(l1 (-400 -1500) (425 1500))
-   rect(l5 (-450 -4890) (425 950))
-   rect(l5 (-400 -950) (425 950))
-  )
-  net(4 name(VSS)
-   rect(l8 (410 1770) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l8 (1220 -730) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l11 (-1640 -1300) (300 1360))
-   rect(l11 (-650 -2160) (2400 800))
-   rect(l11 (-650 0) (300 1360))
-   rect(l11 (-1101 -1761) (2 2))
-   rect(l5 (-651 859) (425 950))
-   rect(l5 (950 -950) (425 950))
-  )
-  net(5
-   rect(l3 (-100 4500) (2600 3500))
-  )
-  net(6 name(SUBSTRATE))
+  # Circuit boundary
+  rect((-100 249) (2600 7751))
 
   # Outgoing pins and their connections to nets
-  pin(1 name(IN))
-  pin(2 name(VDD))
-  pin(3 name(OUT))
-  pin(4 name(VSS))
-  pin(5)
-  pin(6 name(SUBSTRATE))
-
-  # Devices and their connections
-  device(1 D$PMOS
-   device(D$PMOS$1 location(700 0))
-   connect(0 S S)
-   connect(1 S D)
-   connect(0 G G)
-   connect(1 G G)
-   connect(0 D D)
-   connect(1 D S)
-   connect(0 B B)
-   connect(1 B B)
-   location(850 5800)
-   param(L 0.25)
-   param(W 3)
-   param(AS 0.975)
-   param(AD 0.975)
-   param(PS 5.8)
-   param(PD 5.8)
-   terminal(S 2)
-   terminal(G 1)
-   terminal(D 3)
-   terminal(B 5)
-  )
-  device(3 D$NMOS
-   device(D$NMOS$1 location(700 0))
-   connect(0 S S)
-   connect(1 S D)
-   connect(0 G G)
-   connect(1 G G)
-   connect(0 D D)
-   connect(1 D S)
-   connect(0 B B)
-   connect(1 B B)
-   location(850 2135)
-   param(L 0.25)
-   param(W 1.9)
-   param(AS 0.6175)
-   param(AD 0.6175)
-   param(PS 4.15)
-   param(PD 4.15)
-   terminal(S 4)
-   terminal(G 1)
-   terminal(D 3)
-   terminal(B 6)
-  )
+  pin(name(IN))
+  pin(name(VDD))
+  pin(name(OUT))
+  pin(name(VSS))
+  pin()
+  pin(name(BULK))
 
  )
  circuit(RINGO
 
+  # Circuit boundary
+  rect((600 249) (25800 7751))
+
   # Nets with their geometries
   net(1
    rect(l8 (4710 3010) (180 180))
    rect(l11 (-850 -240) (610 300))
-   rect(l1 (-2550 1800) (425 1500))
-   rect(l1 (950 -1500) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
   )
   net(2
    rect(l8 (6510 3010) (180 180))
    rect(l11 (-1140 -240) (900 300))
-   rect(l1 (-1275 1800) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
   )
   net(3
    rect(l8 (19110 3010) (180 180))
    rect(l11 (-1140 -240) (900 300))
-   rect(l1 (-1275 1800) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
   )
   net(4
    rect(l8 (20910 3010) (180 180))
    rect(l11 (-1140 -240) (900 300))
-   rect(l1 (-1275 1800) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
   )
   net(5 name(FB)
    rect(l8 (22710 3010) (180 180))
@@ -508,8 +121,6 @@ layout(
    rect(l13 (-17921 -201) (2 2))
    rect(l13 (-221 -201) (400 400))
    rect(l13 (17740 -400) (400 400))
-   rect(l1 (-245 850) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
   )
   net(6 name(VDD)
    rect(l3 (1100 4500) (1400 3500))
@@ -531,21 +142,7 @@ layout(
    rect(l11 (-750 -1450) (300 1400))
    rect(l11 (-101 -351) (2 2))
    rect(l11 (549 -401) (600 800))
-   rect(l1 (-23625 -2550) (425 1500))
-   rect(l1 (-400 -1500) (425 1500))
-   rect(l1 (1275 -1500) (425 1500))
-   rect(l1 (1375 -1500) (425 1500))
-   rect(l1 (3175 -1500) (425 1500))
-   rect(l1 (-2225 -1500) (425 1500))
-   rect(l1 (3175 -1500) (425 1500))
-   rect(l1 (1375 -1500) (425 1500))
-   rect(l1 (1375 -1500) (425 1500))
-   rect(l1 (1375 -1500) (425 1500))
-   rect(l1 (1375 -1500) (425 1500))
-   rect(l1 (3175 -1500) (425 1500))
-   rect(l1 (950 -1500) (425 1500))
-   rect(l1 (-3600 -1500) (425 1500))
-   rect(l9 (-19575 -450) (500 1500))
+   rect(l9 (-24850 -1500) (500 1500))
    rect(l9 (22900 -1500) (500 1500))
   )
   net(7 name(OUT)
@@ -553,10 +150,6 @@ layout(
    rect(l12 (-260 -260) (200 200))
    rect(l13 (-101 -101) (2 2))
    rect(l13 (-201 -201) (400 400))
-   rect(l1 (-625 850) (425 1500))
-   rect(l1 (-400 -1500) (425 1500))
-   rect(l5 (-450 -4890) (425 950))
-   rect(l5 (-400 -950) (425 950))
   )
   net(8 name(ENABLE)
    rect(l8 (2510 3010) (180 180))
@@ -581,33 +174,16 @@ layout(
    rect(l11 (-750 -1450) (1200 800))
    rect(l11 (-551 -401) (2 2))
    rect(l11 (549 -401) (600 800))
-   rect(l5 (-24300 460) (425 950))
-   rect(l5 (1975 -950) (425 950))
-   rect(l5 (1375 -950) (425 950))
-   rect(l5 (3175 -950) (425 950))
-   rect(l5 (-2225 -950) (425 950))
-   rect(l5 (3175 -950) (425 950))
-   rect(l5 (1375 -950) (425 950))
-   rect(l5 (1375 -950) (425 950))
-   rect(l5 (1375 -950) (425 950))
-   rect(l5 (1375 -950) (425 950))
-   rect(l5 (3175 -950) (425 950))
-   rect(l5 (950 -950) (425 950))
-   rect(l5 (-3600 -950) (425 950))
-   rect(l10 (-19575 -2210) (500 1500))
+   rect(l10 (-24850 -800) (500 1500))
    rect(l10 (22900 -1500) (500 1500))
   )
   net(10
    rect(l8 (8310 3010) (180 180))
    rect(l11 (-1140 -240) (900 300))
-   rect(l1 (-1275 1800) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
   )
   net(11
    rect(l8 (17310 3010) (180 180))
    rect(l11 (-1140 -240) (900 300))
-   rect(l1 (-1275 1800) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
   )
   net(12)
   net(13)
@@ -734,172 +310,36 @@ reference(
  # Circuits are the hierarchical building blocks of the netlist.
  circuit(ND2X1
 
-  # Nets
-  net(1 name(VDD))
-  net(2 name(OUT))
-  net(3 name(VSS))
-  net(4 name(NWELL))
-  net(5 name(B))
-  net(6 name(A))
-  net(7 name(BULK))
-  net(8 name('1'))
-
   # Outgoing pins and their connections to nets
-  pin(1)
-  pin(2)
-  pin(3)
-  pin(4)
-  pin(5)
-  pin(6)
-  pin(7)
-
-  # Devices and their connections
-  device(1 PMOS
-   name($1)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 2)
-   terminal(G 6)
-   terminal(D 1)
-   terminal(B 4)
-  )
-  device(2 PMOS
-   name($2)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 1)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(3 NMOS
-   name($3)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 3)
-   terminal(G 6)
-   terminal(D 8)
-   terminal(B 7)
-  )
-  device(4 NMOS
-   name($4)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 8)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 7)
-  )
+  pin()
+  pin()
+  pin()
+  pin()
+  pin()
+  pin()
+  pin()
 
  )
  circuit(INVX1
 
-  # Nets
-  net(1 name(VDD))
-  net(2 name(OUT))
-  net(3 name(VSS))
-  net(4 name(NWELL))
-  net(5 name(IN))
-  net(6 name(BULK))
-
   # Outgoing pins and their connections to nets
-  pin(1)
-  pin(2)
-  pin(3)
-  pin(4)
-  pin(5)
-  pin(6)
-
-  # Devices and their connections
-  device(1 PMOS
-   name($1)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 1)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(2 NMOS
-   name($2)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 3)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 6)
-  )
+  pin()
+  pin()
+  pin()
+  pin()
+  pin()
+  pin()
 
  )
  circuit(INVX2
 
-  # Nets
-  net(1 name(VDD))
-  net(2 name(OUT))
-  net(3 name(VSS))
-  net(4 name(NWELL))
-  net(5 name(IN))
-  net(6 name(BULK))
-
   # Outgoing pins and their connections to nets
-  pin(1)
-  pin(2)
-  pin(3)
-  pin(4)
-  pin(5)
-  pin(6)
-
-  # Devices and their connections
-  device(1 PMOS
-   name($1)
-   param(L 0.25)
-   param(W 3)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 1)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(2 NMOS
-   name($2)
-   param(L 0.25)
-   param(W 1.9)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 3)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 6)
-  )
+  pin()
+  pin()
+  pin()
+  pin()
+  pin()
+  pin()
 
  )
  circuit(RINGO
@@ -1034,61 +474,33 @@ reference(
 xref(
  circuit(INVX1 INVX1 match
   xref(
-   net(4 4 match)
-   net(5 5 match)
-   net(2 2 match)
-   net(6 6 match)
-   net(1 1 match)
-   net(3 3 match)
    pin(3 3 match)
+   pin(5 5 match)
    pin(4 4 match)
    pin(1 1 match)
-   pin(5 5 match)
    pin(0 0 match)
    pin(2 2 match)
-   device(1 1 match)
-   device(2 2 match)
   )
  )
  circuit(INVX2 INVX2 match
   xref(
-   net(5 4 match)
-   net(1 5 match)
-   net(3 2 match)
-   net(6 6 match)
-   net(2 1 match)
-   net(4 3 match)
-   pin(4 3 match)
-   pin(0 4 match)
-   pin(2 1 match)
+   pin(4 4 match)
    pin(5 5 match)
-   pin(1 0 match)
-   pin(3 2 match)
-   device(1 1 match)
-   device(3 2 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   pin(1 1 match)
+   pin(3 3 match)
   )
  )
  circuit(ND2X1 ND2X1 match
   xref(
-   net(8 8 match)
-   net(4 4 match)
-   net(6 6 match)
-   net(5 5 match)
-   net(2 2 match)
-   net(7 7 match)
-   net(1 1 match)
-   net(3 3 match)
    pin(3 3 match)
    pin(5 5 match)
    pin(4 4 match)
-   pin(1 1 match)
    pin(6 6 match)
+   pin(1 1 match)
    pin(0 0 match)
    pin(2 2 match)
-   device(1 1 match)
-   device(2 2 match)
-   device(3 3 match)
-   device(4 4 match)
   )
  )
  circuit(RINGO RINGO match
@@ -1106,13 +518,13 @@ xref(
    net(8 4 match)
    net(5 3 match)
    net(7 5 match)
-   net(6 2 match)
-   net(9 1 match)
+   net(6 1 warning)
+   net(9 2 warning)
    pin(3 3 match)
    pin(0 2 match)
    pin(2 4 match)
-   pin(1 1 match)
-   pin(4 0 match)
+   pin(1 0 match)
+   pin(4 1 match)
    circuit(1 1 match)
    circuit(5 10 match)
    circuit(6 11 match)