From 008302122071d0314664659019875f0a205f219f Mon Sep 17 00:00:00 2001
From: Matthias Koefferlein <matthias@koefferlein.de>
Date: Sat, 6 Aug 2022 23:44:06 +0200
Subject: [PATCH] [Consider merging] Some refactoring of L2N and LVSDB readers
 for more future compatibility

---
 src/db/db/dbLayoutToNetlistFormatDefs.h       | 105 +--
 src/db/db/dbLayoutToNetlistReader.cc          | 209 ++++--
 src/db/db/dbLayoutToNetlistReader.h           |  12 +-
 src/db/db/dbLayoutVsSchematicFormatDefs.cc    |  14 +
 src/db/db/dbLayoutVsSchematicFormatDefs.h     | 117 +--
 src/db/db/dbLayoutVsSchematicReader.cc        |  32 +-
 .../dbLayoutToNetlistReaderTests.cc           |  24 +
 src/db/unit_tests/dbLayoutVsSchematicTests.cc |  16 +
 testdata/algo/l2n_reader_5.l2n                | 452 ++++++++++++
 testdata/algo/l2n_reader_au_5.l2n             | 487 +++++++++++++
 testdata/algo/lvs_test3.lvsdb                 | 687 ++++++++++++++++++
 testdata/algo/lvs_test3_au.lvsdb              | 673 +++++++++++++++++
 12 files changed, 2651 insertions(+), 177 deletions(-)
 create mode 100644 testdata/algo/l2n_reader_5.l2n
 create mode 100644 testdata/algo/l2n_reader_au_5.l2n
 create mode 100644 testdata/algo/lvs_test3.lvsdb
 create mode 100644 testdata/algo/lvs_test3_au.lvsdb

diff --git a/src/db/db/dbLayoutToNetlistFormatDefs.h b/src/db/db/dbLayoutToNetlistFormatDefs.h
index d77386a2d..428eaaeaa 100644
--- a/src/db/db/dbLayoutToNetlistFormatDefs.h
+++ b/src/db/db/dbLayoutToNetlistFormatDefs.h
@@ -46,55 +46,76 @@ namespace db
  *  The file follows the declaration-before-use principle
  *  (circuits before subcircuits, nets before use ...)
  *
- *  Global statements:
+ *  Main body:
+ *    [version|description|unit|top|layer|connect|global|circuit|class|device|any]*
  *
+ *  [version]:
  *    version(<number>)             - file format version [short key: V]
+ *
+ *  [description]:
  *    description(<text>)           - an arbitrary description text [short key: B]
+ *
+ *  [unit]:
  *    unit(<unit>)                  - specifies the database unit [short key: U]
+ *
+ *  [top]:
  *    top(<circuit>)                - specifies the name of the top circuit [short key: W]
+ *
+ *  [layer]:
  *    layer(<name> <source-spec>?)  - define a layer [short key: L]
+ *
+ *  [connect]:
  *    connect(<layer1> <name> ...)  - connects layer1 with the following layers [short key: C]
+ *
+ *  [global]:
  *    global(<layer> <net-name> ...)
  *                                  - connects the shapes of the layer with the given global
  *                                    nets [short key: G]
+ *
+ *  [circuit]:
  *    circuit(<name> [circuit-def]) - circuit (cell) [short key: X]
+ *
+ *  [class]:
  *    class(<name> <template> [template-def])  - a device class definition (template: RES,CAP,...) [short key: K]
- *    device(<name> <class> [device-abstract-def])
+ *
+ *  [device]:
+ *    device(<name> <class> [device-abstract-terminal|any]*)
  *                                  - device abstract [short key: D]
  *
  *  [circuit-def]:
+ *    [boundary|property|circuit-net|circuit-pin|circuit-device|subcircuit|any]*
  *
- *    [boundary-def]
- *
- *    [property-def]*
- *
- *    net(<id> [name]? [property-def]* [geometry-def]*)
+ *  [circuit-net]:
+ *    net(<id> [name]? [geometries-def])
  *                                  - net geometry [short key: N]
  *                                    A net declaration shall be there also if no geometry
  *                                    is present. The ID is a numerical shortcut for the net.
+ *
+ *  [circuit-pin]:
  *    pin(<net-id> [name]?)         - outgoing pin connection [short key: P]
  *                                    Statement order specifies pin order.
- *    device(<id> <abstract-or-class> [name]? [combined-device]* [terminal-route]* [device-def])
+ *
+ *  [circuit-device]:
+ *    device(<id> <abstract-or-class> [name|trans|combined-device|terminal-route|param|device-terminal|any]*)
  *                                  - device with connections [short key: D]
- *    circuit(<id> [name]? [subcircuit-def])
+ *
+ *  [subcircuit]:
+ *    circuit(<id> [name]? [property|trans|subcircuit-pin|any])
  *                                  - subcircuit with connections [short key: X]
  *
- *  [boundary-def]:
- *
- *    polygon([coord] ...)          - defines a polygon [short key: Q]
+ *  [boundary]:
+ *    polygon([coord] ...) |        - defines a polygon [short key: Q]
  *                                    "*" for <x> or <y> means take previous
  *    rect([coord] [coord])         - defines a rectangle [short key: R]
  *                                    coordinates are bottom/left and top/right
  *
  *  [combined-device]:
- *
- *    device(<abstract> [trans-def])
+ *    device(<abstract> [trans])
  *                                  - specifies an additional device component
  *                                    (for combined devices) with abstract <abstract>
  *                                    and offset dx, dy.
  *
  *  [terminal-route]:
- *
  *    connect(<device-index> <outer-terminal-name> <inner-terminal-name>)
  *                                  - connects the outer terminal with the terminal
  *                                    of the device component with <device-index>:
@@ -102,68 +123,70 @@ namespace db
  *                                    device etc.
  *
  *  [name]:
- *
  *    name(<name>)                  - specify net name [short key: I]
  *
- *  [property-def]:
+ *  [geometries-def]:
+ *    [property|polygon|rect|text|any]*
  *
+ *  [property]:
  *    property(<prop-name> <prop-value>)
  *                                  - specifies a property value/key pair [short key: F]
  *                                    prop-name and prop-value are variant specifications
  *                                    in klayout notation: #x is an integer, ##y a floating-point
  *                                    value, a word or quoted literal is a string.
  *
- *  [geometry-def]:
- *
+ *  [polygon]:
  *    polygon(<layer> [coord] ...)  - defines a polygon [short key: Q]
  *                                    "*" for <x> or <y> means take previous
+ *
+ *  [rect]:
  *    rect(<layer> [coord] [coord]) - defines a rectangle [short key: R]
  *                                    coordinates are bottom/left and top/right
+ *
+ *  [text]:
  *    text(<layer> [text] [coord])  - defines a rectangle [short key: J]
  *
- *  [coord]
- *
+ *  [coord]:
  *    <x> <y>                       - absolute coordinates
  *    (<x> <y>)                     - relative coordinates (reference is reset to 0,0
  *                                    for each net or terminal in device abstract)
  *
  *  [template-def]:
+ *    [template-param|template-terminal|any]*
  *
+ *  [template-param]:
  *    param(<name> <primary>? <default-value>*)    - defines a template parameter [short key: E]
  *                                    ('primary' is a value: 0 or 1)
+ *
+ *  [template-terminal]:
  *    terminal(<name>)              - defines a terminal [short key: T]
  *
- *  [device-abstract-def]:
- *
- *    [device-abstract-terminal-def]*
- *
- *  [device-abstract-terminal-def]:
- *
- *    terminal(<terminal-name> [geometry-def]*)
+ *  [device-abstract-terminal]:
+ *    terminal(<terminal-name> [geometries-def])
  *                                  - specifies the terminal geometry [short key: T]
  *
- *  [device-def]:
- *
- *    [property-def]*               - user properties
- *    [trans-def]                   - location of the device
- *                                    must be before terminal
+ *  [param]:
  *    param(<name> <value>)         - defines a parameter [short key: E]
+ *
+ *  [device-terminal]:
  *    terminal(<terminal-name> <net-id>)
- *                                  - specifies connection of the terminal with
- *                                    a net (short key: T)
+ *                                  - specifies connection of the terminal with a net (short key: T)
  *
- *  [subcircuit-def]:
- *
- *    [property-def]*               - user properties
- *    [trans-def]                   - location of the subcircuit
+ *  [subcircuit-pin]:
  *    pin(<pin-id> <net-id>)        - specifies connection of the pin with a net [short key: P]
  *
- *  [trans-def]:
- *
+ *  [trans]:
  *    location(<x> <y>)             - location of the instance [short key: Y]
  *    rotation(<angle>)             - rotation angle (in degree, default is 0) [short key: O]
  *    mirror                        - if specified, the instance is mirrored before rotation [short key: M]
  *    scale(<mag>)                  - magnification (default is 1) [short key: S]
+ *
+ *  [any]:
+ *    * |
+ *    <token> |
+ *    <token> ( [any]* ) |
+ *    <float> |
+ *    <quoted-string>
  */
 
 namespace l2n_std_format
diff --git a/src/db/db/dbLayoutToNetlistReader.cc b/src/db/db/dbLayoutToNetlistReader.cc
index 30fab09e2..96bcc1d90 100644
--- a/src/db/db/dbLayoutToNetlistReader.cc
+++ b/src/db/db/dbLayoutToNetlistReader.cc
@@ -97,6 +97,13 @@ LayoutToNetlistStandardReader::read_int ()
   return i;
 }
 
+bool
+LayoutToNetlistStandardReader::try_read_int (int &i)
+{
+  i = 0;
+  return m_ex.try_read (i);
+}
+
 db::Coord
 LayoutToNetlistStandardReader::read_coord ()
 {
@@ -133,6 +140,50 @@ LayoutToNetlistStandardReader::skip ()
   }
 }
 
+void LayoutToNetlistStandardReader::skip_element ()
+{
+  std::string s;
+  double f;
+
+  if (m_ex.try_read_word (s)) {
+
+    //  skip bracket elements after token key
+    Brace br (this);
+    while (br) {
+      skip_element ();
+    }
+    br.done ();
+
+  } else if (m_ex.test ("*")) {
+
+    //  asterisk is allowed as element (e.g. inside point)
+
+  } else if (m_ex.try_read_quoted (s)) {
+
+    //  skip string
+
+  } else if (m_ex.try_read (f)) {
+
+    //  skip numeric value
+
+  } else {
+
+    Brace br (this);
+    if (br) {
+
+      //  skip bracket elements without token
+      while (br) {
+        skip_element ();
+      }
+      br.done ();
+
+    } else {
+      throw tl::Exception (tl::to_string (tr ("Unexpected token")));
+    }
+
+  }
+}
+
 void LayoutToNetlistStandardReader::do_read (db::LayoutToNetlist *l2n)
 {
   tl::SelfTimer timer (tl::verbosity () >= 21, tl::to_string (tr ("File read: ")) + m_path);
@@ -153,7 +204,7 @@ static db::Region &layer_by_name (db::LayoutToNetlist *l2n, const std::string &n
   return *l;
 }
 
-void LayoutToNetlistStandardReader::read_netlist (db::Netlist *netlist, db::LayoutToNetlist *l2n, bool nested, std::map<const db::Circuit *, ObjectMap> *map_per_circuit)
+void LayoutToNetlistStandardReader::read_netlist (db::Netlist *netlist, db::LayoutToNetlist *l2n, LayoutToNetlistStandardReader::Brace *nested, std::map<const db::Circuit *, ObjectMap> *map_per_circuit)
 {
   m_dbu = 0.001;
   int version = 0;
@@ -179,7 +230,7 @@ void LayoutToNetlistStandardReader::read_netlist (db::Netlist *netlist, db::Layo
 
   db::LayoutLocker layout_locker (l2n ? l2n->internal_layout () : 0);
 
-  while (! at_end ()) {
+  while (nested ? *nested : ! at_end ()) {
 
     if (test (skeys::version_key) || test (lkeys::version_key)) {
 
@@ -289,7 +340,7 @@ void LayoutToNetlistStandardReader::read_netlist (db::Netlist *netlist, db::Layo
           br.done ();
 
         } else {
-          throw tl::Exception (tl::to_string (tr ("Invalid keyword")));
+          skip_element ();
         }
 
       }
@@ -369,7 +420,7 @@ void LayoutToNetlistStandardReader::read_netlist (db::Netlist *netlist, db::Layo
         } else if (at_end ()) {
           throw tl::Exception (tl::to_string (tr ("Unexpected end of file inside circuit definition (rect, polygon, net, pin, device or circuit expected)")));
         } else {
-          throw tl::Exception (tl::to_string (tr ("Invalid keyword inside circuit definition (rect, polygon, net, pin, device or circuit expected)")));
+          skip_element ();
         }
 
       }
@@ -430,19 +481,17 @@ void LayoutToNetlistStandardReader::read_netlist (db::Netlist *netlist, db::Layo
         } else if (at_end ()) {
           throw tl::Exception (tl::to_string (tr ("Unexpected end of file inside device abstract definition (terminal expected)")));
         } else {
-          throw tl::Exception (tl::to_string (tr ("Invalid keyword inside device abstract definition (terminal expected)")));
+          skip_element ();
         }
 
       }
 
       br.done ();
 
-    } else if (nested) {
-      break;
     } else if (at_end ()) {
-      throw tl::Exception (tl::to_string (tr ("Unexpected end of file")));
+      throw tl::Exception (tl::to_string (tr ("Unexpected end of file inside device abstract definition (terminal expected)")));
     } else {
-      throw tl::Exception (tl::to_string (tr ("Invalid keyword")));
+      skip_element ();
     }
 
   }
@@ -450,6 +499,10 @@ void LayoutToNetlistStandardReader::read_netlist (db::Netlist *netlist, db::Layo
   if (l2n) {
     l2n->set_netlist_extracted ();
   }
+
+  if (version > 1) {
+    throw tl::Exception (tl::to_string (tr ("This program version only supports version 1 of the L2N DB format. File version is: ")) + tl::to_string (version));
+  }
 }
 
 db::Point
@@ -490,65 +543,6 @@ LayoutToNetlistStandardReader::read_property (db::NetlistObject *obj)
   br.done ();
 }
 
-std::pair<unsigned int, NetShape> LayoutToNetlistStandardReader::read_geometry(db::LayoutToNetlist *l2n)
-{
-  std::string lname;
-
-  if (test (skeys::rect_key) || test (lkeys::rect_key)) {
-
-    Brace br (this);
-
-    read_word_or_quoted (lname);
-    unsigned int lid = l2n->layer_of (layer_by_name (l2n, lname));
-
-    db::Point lb = read_point ();
-    db::Point rt = read_point ();
-    db::Box box (lb, rt);
-
-    br.done ();
-
-    return std::make_pair (lid, db::PolygonRef (db::Polygon (box), l2n->internal_layout ()->shape_repository ()));
-
-  } else if (test (skeys::polygon_key) || test (lkeys::polygon_key)) {
-
-    Brace br (this);
-
-    read_word_or_quoted (lname);
-    unsigned int lid = l2n->layer_of (layer_by_name (l2n, lname));
-
-    std::vector<db::Point> pt;
-    while (br) {
-      pt.push_back (read_point ());
-    }
-    br.done ();
-
-    db::Polygon poly;
-    poly.assign_hull (pt.begin (), pt.end ());
-    return std::make_pair (lid, db::PolygonRef (poly, l2n->internal_layout ()->shape_repository ()));
-
-  } else if (test (skeys::text_key) || test (lkeys::text_key)) {
-
-    Brace br (this);
-
-    read_word_or_quoted (lname);
-    unsigned int lid = l2n->layer_of (layer_by_name (l2n, lname));
-
-    std::string text;
-    read_word_or_quoted (text);
-
-    db::Point pt = read_point ();
-
-    br.done ();
-
-    return std::make_pair (lid, db::TextRef (db::Text (text, db::Trans (pt - db::Point ())), l2n->internal_layout ()->shape_repository ()));
-
-  } else if (at_end ()) {
-    throw tl::Exception (tl::to_string (tr ("Unexpected end of file (polygon or rect expected)")));
-  } else {
-    throw tl::Exception (tl::to_string (tr ("Invalid keyword (polygon or rect expected)")));
-  }
-}
-
 db::Box
 LayoutToNetlistStandardReader::read_rect ()
 {
@@ -587,14 +581,75 @@ void
 LayoutToNetlistStandardReader::read_geometries (db::NetlistObject *obj, Brace &br, db::LayoutToNetlist *l2n, db::local_cluster<db::NetShape> &lc, db::Cell &cell)
 {
   m_ref = db::Point ();
+  std::string lname;
 
   while (br) {
+
     if (test (skeys::property_key) || test (lkeys::property_key)) {
+
       read_property (obj);
+
+    } else if (test (skeys::rect_key) || test (lkeys::rect_key)) {
+
+      Brace br (this);
+
+      read_word_or_quoted (lname);
+      unsigned int lid = l2n->layer_of (layer_by_name (l2n, lname));
+
+      db::Point lb = read_point ();
+      db::Point rt = read_point ();
+      db::Box box (lb, rt);
+
+      br.done ();
+
+      NetShape n (db::PolygonRef (db::Polygon (box), l2n->internal_layout ()->shape_repository ()));
+
+      lc.add (n, lid);
+      n.insert_into (cell.shapes (lid));
+
+    } else if (test (skeys::polygon_key) || test (lkeys::polygon_key)) {
+
+      Brace br (this);
+
+      read_word_or_quoted (lname);
+      unsigned int lid = l2n->layer_of (layer_by_name (l2n, lname));
+
+      std::vector<db::Point> pt;
+      while (br) {
+        pt.push_back (read_point ());
+      }
+      br.done ();
+
+      db::Polygon poly;
+      poly.assign_hull (pt.begin (), pt.end ());
+      NetShape n (db::PolygonRef (poly, l2n->internal_layout ()->shape_repository ()));
+
+      lc.add (n, lid);
+      n.insert_into (cell.shapes (lid));
+
+    } else if (test (skeys::text_key) || test (lkeys::text_key)) {
+
+      Brace br (this);
+
+      read_word_or_quoted (lname);
+      unsigned int lid = l2n->layer_of (layer_by_name (l2n, lname));
+
+      std::string text;
+      read_word_or_quoted (text);
+
+      db::Point pt = read_point ();
+
+      br.done ();
+
+      NetShape n (db::TextRef (db::Text (text, db::Trans (pt - db::Point ())), l2n->internal_layout ()->shape_repository ()));
+
+      lc.add (n, lid);
+      n.insert_into (cell.shapes (lid));
+
+    } else if (at_end ()) {
+      throw tl::Exception (tl::to_string (tr ("Unexpected end of file (polygon, text or rect expected)")));
     } else {
-      std::pair<unsigned int, db::NetShape> pr = read_geometry (l2n);
-      lc.add (pr.second, pr.first);
-      pr.second.insert_into (cell.shapes (pr.first));
+      skip_element ();
     }
   }
 }
@@ -641,6 +696,7 @@ LayoutToNetlistStandardReader::read_pin (db::Netlist * /*netlist*/, db::LayoutTo
   db::Net *net = 0;
 
   db::Pin pin;
+  int netid = 0;
 
   while (br) {
 
@@ -660,18 +716,19 @@ LayoutToNetlistStandardReader::read_pin (db::Netlist * /*netlist*/, db::LayoutTo
 
       read_property (&pin);
 
-    } else {
+    } else if (try_read_int (netid)) {
 
       if (net) {
         throw tl::Exception (tl::to_string (tr ("Duplicate net ID")));
       }
 
-      unsigned int netid = (unsigned int) read_int ();
-      net = map.id2net [netid];
+      net = map.id2net [(unsigned int) netid];
       if (!net) {
         throw tl::Exception (tl::to_string (tr ("Not a valid net ID: ")) + tl::to_string (netid));
       }
 
+    } else {
+      skip_element ();
     }
 
   }
@@ -851,7 +908,7 @@ LayoutToNetlistStandardReader::read_device (db::Netlist *netlist, db::LayoutToNe
     } else if (at_end ()) {
       throw tl::Exception (tl::to_string (tr ("Unexpected end of file inside device definition (location, scale, mirror, rotation, param or terminal expected)")));
     } else {
-      throw tl::Exception (tl::to_string (tr ("Invalid keyword inside device definition (location, scale, mirror, rotation, param or terminal expected)")));
+      skip_element ();
     }
 
   }
@@ -1032,7 +1089,7 @@ LayoutToNetlistStandardReader::read_subcircuit (db::Netlist *netlist, db::Layout
     } else if (at_end ()) {
       throw tl::Exception (tl::to_string (tr ("Unexpected end of file inside subcircuit definition (location, rotation, mirror, scale or pin expected)")));
     } else {
-      throw tl::Exception (tl::to_string (tr ("Invalid keyword inside subcircuit definition (location, rotation, mirror, scale or pin expected)")));
+      skip_element ();
     }
 
   }
diff --git a/src/db/db/dbLayoutToNetlistReader.h b/src/db/db/dbLayoutToNetlistReader.h
index 0c4e75f22..fb81d7452 100644
--- a/src/db/db/dbLayoutToNetlistReader.h
+++ b/src/db/db/dbLayoutToNetlistReader.h
@@ -44,6 +44,11 @@ namespace l2n_std_reader {
     operator bool ();
     void done ();
 
+    bool has_brace () const
+    {
+      return m_has_brace;
+    }
+
   private:
     db::LayoutToNetlistStandardReader *mp_reader;
     bool m_checked;
@@ -101,7 +106,7 @@ protected:
   friend class l2n_std_reader::Brace;
   typedef l2n_std_reader::Brace Brace;
 
-  void read_netlist (Netlist *netlist, db::LayoutToNetlist *l2n, bool nested = false, std::map<const db::Circuit *, ObjectMap> *map_per_circuit = 0);
+  void read_netlist (Netlist *netlist, db::LayoutToNetlist *l2n, Brace *nested = 0, std::map<const db::Circuit *, ObjectMap> *map_per_circuit = 0);
   static size_t terminal_id (const db::DeviceClass *device_class, const std::string &tname);
   static std::pair<db::DeviceAbstract *, const db::DeviceClass *> device_model_by_name (db::Netlist *netlist, const std::string &dmname);
 
@@ -126,12 +131,14 @@ protected:
 
   bool test (const std::string &token);
   void expect (const std::string &token);
-  void read_word_or_quoted(std::string &s);
+  void read_word_or_quoted (std::string &s);
   int read_int ();
+  bool try_read_int (int &i);
   db::Coord read_coord ();
   double read_double ();
   bool at_end ();
   void skip ();
+  void skip_element ();
 
   void read_net (Netlist *netlist, db::LayoutToNetlist *l2n, db::Circuit *circuit, ObjectMap &map);
   void read_pin (Netlist *netlist, db::LayoutToNetlist *l2n, db::Circuit *circuit, ObjectMap &map);
@@ -139,7 +146,6 @@ protected:
   void read_subcircuit (Netlist *netlist, db::LayoutToNetlist *l2n, db::Circuit *circuit, ObjectMap &map, std::map<db::CellInstArray, std::list<Connections> > &connections);
   bool read_trans_part (db::DCplxTrans &tr);
   void read_abstract_terminal (db::LayoutToNetlist *l2n, db::DeviceAbstract *dm, db::DeviceClass *dc);
-  std::pair<unsigned int, db::NetShape> read_geometry(db::LayoutToNetlist *l2n);
   void read_property (db::NetlistObject *obj);
   db::Polygon read_polygon ();
   db::Box read_rect ();
diff --git a/src/db/db/dbLayoutVsSchematicFormatDefs.cc b/src/db/db/dbLayoutVsSchematicFormatDefs.cc
index 875429e54..8545bf3f7 100644
--- a/src/db/db/dbLayoutVsSchematicFormatDefs.cc
+++ b/src/db/db/dbLayoutVsSchematicFormatDefs.cc
@@ -34,6 +34,8 @@ namespace lvs_std_format
   DB_PUBLIC std::string LongKeys::reference_key ("reference");
   DB_PUBLIC std::string LongKeys::layout_key ("layout");
   DB_PUBLIC std::string LongKeys::xref_key ("xref");
+  DB_PUBLIC std::string LongKeys::log_key ("log");
+  DB_PUBLIC std::string LongKeys::log_entry_key ("entry");
 
   DB_PUBLIC std::string LongKeys::mismatch_key ("mismatch");
   DB_PUBLIC std::string LongKeys::match_key ("match");
@@ -41,15 +43,27 @@ namespace lvs_std_format
   DB_PUBLIC std::string LongKeys::warning_key ("warning");
   DB_PUBLIC std::string LongKeys::skipped_key ("skipped");
 
+  DB_PUBLIC std::string LongKeys::info_level_key ("info");
+  DB_PUBLIC std::string LongKeys::warning_level_key ("warning");
+  DB_PUBLIC std::string LongKeys::error_level_key ("error");
+
+  //  E, H, I, J, L, M, S, W, X, Z, 0, 1
+
   DB_PUBLIC std::string ShortKeys::reference_key ("H");
   DB_PUBLIC std::string ShortKeys::layout_key ("J");
   DB_PUBLIC std::string ShortKeys::xref_key ("Z");
+  DB_PUBLIC std::string ShortKeys::log_key ("L");
+  DB_PUBLIC std::string ShortKeys::log_entry_key ("M");
 
   DB_PUBLIC std::string ShortKeys::mismatch_key ("0");
   DB_PUBLIC std::string ShortKeys::match_key ("1");
   DB_PUBLIC std::string ShortKeys::nomatch_key ("X");
   DB_PUBLIC std::string ShortKeys::warning_key ("W");
   DB_PUBLIC std::string ShortKeys::skipped_key ("S");
+
+  DB_PUBLIC std::string ShortKeys::info_level_key ("I");
+  DB_PUBLIC std::string ShortKeys::warning_level_key ("W");
+  DB_PUBLIC std::string ShortKeys::error_level_key ("E");
 }
 
 }
diff --git a/src/db/db/dbLayoutVsSchematicFormatDefs.h b/src/db/db/dbLayoutVsSchematicFormatDefs.h
index fd60336ce..17a7a4101 100644
--- a/src/db/db/dbLayoutVsSchematicFormatDefs.h
+++ b/src/db/db/dbLayoutVsSchematicFormatDefs.h
@@ -47,80 +47,81 @@ namespace db
  *  The file follows the declaration-before-use principle
  *  (circuits before subcircuits, nets before use ...)
  *
- *  Global statements:
- *
+ *  Main body:
  *    #%lvsdb-klayout                  - header line identifies format
+ *    [version|description|layout-netlist|reference-netlist|xrefs|any]*
+ *
+ *  [version]:
  *    version(<number>)                - file format version [short key: V]
+ *
+ *  [description]:
  *    description(<text>)              - an arbitrary description text [short key: B]
- *    layout([layout])                 - layout part [short key: J]
- *    reference([reference-def]*)      - reference netlist part [short key: H]
- *    xref([xref-def]*)                - cross-reference part [short key: Z]
  *
- *  [layout]:
+ *  [layout-netlist]:
+ *    layout(...)                      - layout netlist part [short key: J]
+ *                                       Content is the LayoutToNetlist dump without version and description
  *
- *      ...                            - the LayoutToNetlist dump without version and description
+ *  [reference-netlist]:
+ *    reference(...)
+ *                                     - reference netlist part [short key: H]
+ *                                       Content is the Netlist dump (reduced version of LayoutToNetlist)
  *
- *  [reference-def]:
+ *  [xrefs]:
+ *    xref([xref|any]*)                - cross-reference part [short key: Z]
  *
- *    circuit(<name> [netlist-circuit-def]*)
- *                                     - circuit [short key: X]
- *  [netlist-circuit-def]:
- *
- *    net(<id> [net-name]?)            - a net declaration [short key: N]
- *    pin(<name> <net-id>)             - outgoing pin connection [short key: P]
- *    device(<name> [device-def]*)     - device with connections [short key: D]
- *    circuit(<name> [subcircuit-def]*)
- *                                     - subcircuit with connections [short key: X]
- *
- *  [net-name]:
- *
- *    name(<net-name>)                 - specify net name [short key: I]
- *
- *  [device-def]:
- *
- *    terminal(<terminal-name> <net-id>)
- *                                     - specifies connection of the terminal with
- *                                       a net [short key: T]
- *
- *  [subcircuit-def]:
- *
- *    pin(<pin-name> <net-id>)         - specifies connection of the pin with a net [short key: P]
- *
- *  [xref-def]:
- *
- *    circuit([non] [non] [status]? [message]? [circuit-xrefs])
+ *  [xref]:
+ *    circuit([non] [non] [status|message|log|circuit-xrefs|any]*)
  *                                     - circuit pair [short key: X]
  *
- *  [circuit-xrefs]:
- *
- *    xref([pair]*)                    - circuit cross-reference part [short key: Z]
- *
- *  [pair]
- *
- *    pin([ion] [ion] [status]? [message]?)       - a pin pair [short key: P]
- *    device([ion] [ion] [status]? [message]?)    - a device pair [short key: D]
- *    circuit([ion] [ion] [status]? [message]?)   - a subcircuit pair [short key: X]
- *    net([ion] [ion] [status]? [message]?)       - a net pair [short key: N]
- *
  *  [non]
- *
  *    <name> | ()
  *
- *  [ion]
+ *  [log]:
+ *    log([log-entry]*)                - log entries [short key: L]
  *
+ *  [log-entry]:
+ *    entry([level] <name> [any]*)     - log entry [short key: M]
+ *
+ *  [level]:
+ *    info |                           - [short key: I]
+ *    warning |                        - [short key: W]
+ *    error                            - [short key: E]
+ *
+ *  [circuit-xrefs]:
+ *    xref([xref-pin|xref-device|xref-circuit|xref-net|any]*)
+ *                                     - circuit cross-reference part [short key: Z]
+ *
+ *  [xref-pin]:
+ *    pin([ion] [ion] [status]? [message]? [any]*)       - a pin pair [short key: P]
+ *
+ *  [xref-device]:
+ *    device([ion] [ion] [status]? [message]? [any]*)    - a device pair [short key: D]
+ *
+ *  [xref-circuit]:
+ *    circuit([ion] [ion] [status]? [message]? [any]*)   - a subcircuit pair [short key: X]
+ *
+ *  [xref-net]:
+ *    net([ion] [ion] [status]? [message]? [any]*)       - a net pair [short key: N]
+ *
+ *  [ion]:
  *    <id> | ()
  *
- *  [message]
- *
+ *  [message]:
  *    description(<name>)              - error description [short key: B]
  *
- *  [status]
- *
+ *  [status]:
  *    mismatch |                       - [short key: 0]
  *    match |                          - [short key: 1]
  *    nomatch |                        - [short key: X]
  *    warning |                        - [short key: W]
  *    skipped                          - [short key: S]
+ *
+ *  [any]:
+ *    * |
+ *    <token> |
+ *    <token> ( [any]* ) |
+ *    <float> |
+ *    <quoted-string>
  */
 
 namespace lvs_std_format
@@ -132,12 +133,18 @@ namespace lvs_std_format
     static std::string reference_key;
     static std::string layout_key;
     static std::string xref_key;
+    static std::string log_key;
+    static std::string log_entry_key;
 
     static std::string mismatch_key;
     static std::string match_key;
     static std::string nomatch_key;
     static std::string warning_key;
     static std::string skipped_key;
+
+    static std::string info_level_key;
+    static std::string warning_level_key;
+    static std::string error_level_key;
   };
 
   struct DB_PUBLIC LongKeys
@@ -147,12 +154,18 @@ namespace lvs_std_format
     static std::string reference_key;
     static std::string layout_key;
     static std::string xref_key;
+    static std::string log_key;
+    static std::string log_entry_key;
 
     static std::string mismatch_key;
     static std::string match_key;
     static std::string nomatch_key;
     static std::string warning_key;
     static std::string skipped_key;
+
+    static std::string info_level_key;
+    static std::string warning_level_key;
+    static std::string error_level_key;
   };
 
   template <bool Short> struct DB_PUBLIC keys;
diff --git a/src/db/db/dbLayoutVsSchematicReader.cc b/src/db/db/dbLayoutVsSchematicReader.cc
index 688934b62..f7924742a 100644
--- a/src/db/db/dbLayoutVsSchematicReader.cc
+++ b/src/db/db/dbLayoutVsSchematicReader.cc
@@ -81,14 +81,14 @@ void LayoutVsSchematicStandardReader::read_netlist (db::LayoutVsSchematic *lvs)
     } else if (test (skeys::layout_key) || test (lkeys::layout_key)) {
 
       Brace br (this);
-      LayoutToNetlistStandardReader::read_netlist (0, lvs, true /*nested*/, &m_map_per_circuit_a);
+      LayoutToNetlistStandardReader::read_netlist (0, lvs, &br, &m_map_per_circuit_a);
       br.done ();
 
     } else if (test (skeys::reference_key) || test (lkeys::reference_key)) {
 
       Brace br (this);
       std::unique_ptr<db::Netlist> netlist (new db::Netlist ());
-      LayoutToNetlistStandardReader::read_netlist (netlist.get (), 0, true /*nested*/, &m_map_per_circuit_b);
+      LayoutToNetlistStandardReader::read_netlist (netlist.get (), 0, &br, &m_map_per_circuit_b);
       lvs->set_reference_netlist (netlist.release ());
       br.done ();
 
@@ -106,10 +106,14 @@ void LayoutVsSchematicStandardReader::read_netlist (db::LayoutVsSchematic *lvs)
     } else if (at_end ()) {
       throw tl::Exception (tl::to_string (tr ("Unexpected end of file")));
     } else {
-      throw tl::Exception (tl::to_string (tr ("Invalid keyword")));
+      skip_element ();
     }
 
   }
+
+  if (version > 1) {
+    throw tl::Exception (tl::to_string (tr ("This program version only supports version 1 of the LVS DB format. File version is: ")) + tl::to_string (version));
+  }
 }
 
 bool LayoutVsSchematicStandardReader::read_message (std::string &msg)
@@ -162,7 +166,7 @@ void LayoutVsSchematicStandardReader::read_xrefs_for_circuits (db::NetlistCrossR
     } else if (at_end ()) {
       throw tl::Exception (tl::to_string (tr ("Unexpected end of file inside circuit definition (net, pin, device or circuit expected)")));
     } else {
-      throw tl::Exception (tl::to_string (tr ("Invalid keyword inside circuit definition (net, pin, device or circuit expected)")));
+      skip_element ();
     }
 
   }
@@ -214,7 +218,7 @@ void LayoutVsSchematicStandardReader::read_xref (db::NetlistCrossReference *xref
         } else if (at_end ()) {
           throw tl::Exception (tl::to_string (tr ("Unexpected end of file inside circuit definition (status keyword of xrefs expected)")));
         } else {
-          throw tl::Exception (tl::to_string (tr ("Invalid keyword inside circuit definition (status keyword of xrefs expected)")));
+          skip_element ();
         }
 
       }
@@ -223,6 +227,8 @@ void LayoutVsSchematicStandardReader::read_xref (db::NetlistCrossReference *xref
 
       br.done ();
 
+    } else {
+      skip_element ();
     }
 
   }
@@ -344,6 +350,10 @@ void LayoutVsSchematicStandardReader::read_net_pair (db::NetlistCrossReference *
   read_status (status);
   read_message (msg);
 
+  while (br) {
+    skip_element ();
+  }
+
   br.done ();
 
   xref->gen_nets (net_by_numerical_id (circuit_a, ion_a, m_map_per_circuit_a), net_by_numerical_id (circuit_b, ion_b, m_map_per_circuit_b), status, msg);
@@ -362,6 +372,10 @@ void LayoutVsSchematicStandardReader::read_pin_pair (db::NetlistCrossReference *
   read_status (status);
   read_message (msg);
 
+  while (br) {
+    skip_element ();
+  }
+
   br.done ();
 
   xref->gen_pins (pin_by_numerical_id (circuit_a, ion_a), pin_by_numerical_id (circuit_b, ion_b), status, msg);
@@ -380,6 +394,10 @@ void LayoutVsSchematicStandardReader::read_device_pair (db::NetlistCrossReferenc
   read_status (status);
   read_message (msg);
 
+  while (br) {
+    skip_element ();
+  }
+
   br.done ();
 
   xref->gen_devices (device_by_numerical_id (circuit_a, ion_a, m_map_per_circuit_a), device_by_numerical_id (circuit_b, ion_b, m_map_per_circuit_b), status, msg);
@@ -398,6 +416,10 @@ void LayoutVsSchematicStandardReader::read_subcircuit_pair (db::NetlistCrossRefe
   read_status (status);
   read_message (msg);
 
+  while (br) {
+    skip_element ();
+  }
+
   br.done ();
 
   xref->gen_subcircuits (subcircuit_by_numerical_id (circuit_a, ion_a, m_map_per_circuit_a), subcircuit_by_numerical_id (circuit_b, ion_b, m_map_per_circuit_b), status, msg);
diff --git a/src/db/unit_tests/dbLayoutToNetlistReaderTests.cc b/src/db/unit_tests/dbLayoutToNetlistReaderTests.cc
index 6f29b26c5..a51174990 100644
--- a/src/db/unit_tests/dbLayoutToNetlistReaderTests.cc
+++ b/src/db/unit_tests/dbLayoutToNetlistReaderTests.cc
@@ -473,3 +473,27 @@ TEST(4_ReaderCombinedDevices)
   }
 }
 
+TEST(5_ReaderFuture)
+{
+  db::LayoutToNetlist l2n;
+
+  std::string in_path = tl::combine_path (tl::combine_path (tl::testdata (), "algo"), "l2n_reader_5.l2n");
+  tl::InputStream is_in (in_path);
+
+  db::LayoutToNetlistStandardReader reader (is_in);
+  reader.read (&l2n);
+
+  //  verify against the input
+
+  std::string path = tmp_file ("tmp.txt");
+  {
+    tl::OutputStream stream (path);
+    db::LayoutToNetlistStandardWriter writer (stream, false);
+    writer.write (&l2n);
+  }
+
+  std::string au_path = tl::combine_path (tl::combine_path (tl::testdata (), "algo"), "l2n_reader_au_5.l2n");
+
+  compare_text_files (path, au_path);
+}
+
diff --git a/src/db/unit_tests/dbLayoutVsSchematicTests.cc b/src/db/unit_tests/dbLayoutVsSchematicTests.cc
index f617ae11d..3bf8fa629 100644
--- a/src/db/unit_tests/dbLayoutVsSchematicTests.cc
+++ b/src/db/unit_tests/dbLayoutVsSchematicTests.cc
@@ -443,3 +443,19 @@ TEST(2_FlowWithErrors)
   compare_lvsdbs (_this, path2, au_path2);
 }
 
+TEST(3_ReaderFuture)
+{
+  db::LayoutVsSchematic lvs;
+
+  std::string in_path = tl::combine_path (tl::combine_path (tl::testdata (), "algo"), "lvs_test3.lvsdb");
+  lvs.load (in_path);
+
+  //  verify against the input
+
+  std::string path = tmp_file ("tmp.txt");
+  lvs.save (path, false);
+
+  std::string au_path = tl::combine_path (tl::combine_path (tl::testdata (), "algo"), "lvs_test3_au.lvsdb");
+
+  compare_text_files (path, au_path);
+}
diff --git a/testdata/algo/l2n_reader_5.l2n b/testdata/algo/l2n_reader_5.l2n
new file mode 100644
index 000000000..5513bfa01
--- /dev/null
+++ b/testdata/algo/l2n_reader_5.l2n
@@ -0,0 +1,452 @@
+#%l2n-klayout
+W(RINGO)
+U(0.001)
+L($3)
+L($9)
+L($4)
+L($5)
+L($6)
+L($10)
+L($7)
+L($8)
+L($11)
+L($1)
+L($2)
+C($3 $3 $9 $5)
+C($9 $3)
+C($4 $4 $6 $1 $2)
+C($5 $3 $5 $6)
+C($6 $4 $5 $6 $10 $7)
+C($10 $6)
+C($7 $6 $7 $8)
+C($8 $7 $8 $11)
+C($11 $8)
+C($1 $4 $1)
+C($2 $4 $2)
+D(D$PMOS PMOS
+ kk(1 "hello" jj(1 5 7))   # invalid
+ T(S
+  R($1 -650 -475 -125 475)
+ )
+ T(G
+  R($3 -125 -475 125 475)
+ )
+ kk   # invalid
+ T(D
+  R($1 125 -475 675 475)
+ )
+ kk ( 1 "hello" jj 2.5 * (1 5 "hello") )   # invalid
+)
+D(D$PMOS$1 PMOS
+ T(S
+  R($1 -675 -475 -125 475)
+ )
+ T(G
+  R($3 -125 -475 125 475)
+ )
+ T(D
+  R($1 125 -475 650 475)
+ )
+)
+D(D$NMOS NMOS
+ T(S
+  R($2 -650 -475 -125 475)
+ )
+ T(G
+  R($3 -125 -475 125 475)
+ )
+ T(D
+  R($2 125 -475 675 475)
+ )
+)
+D(D$NMOS$1 NMOS
+ T(S
+  R($2 -675 -475 -125 475)
+ )
+ T(G
+  R($3 -125 -475 125 475)
+ )
+ T(D
+  R($2 125 -475 650 475)
+ )
+)
+X(INV2
+ kk   # invalid
+ N(1 I(NIN)
+ kk   # invalid
+  R($3 -525 -250 -275 2250)
+  R($3 -1700 1620 -400 1980)
+  R($3 -525 -800 -275 800)
+  R($3 -525 2000 -275 3600)
+  R($9 -801 1799 -799 1801)
+  R($5 -1630 1690 -1410 1910)
+ kk   # invalid
+ )
+ N(2
+  R($3 275 -250 525 2250)
+  R($3 220 820 580 1180)
+  R($3 275 2000 525 3600)
+  R($3 275 -800 525 800)
+  R($4 -910 2490 -690 2710)
+  R($4 -910 2890 -690 3110)
+  R($4 -910 -310 -690 -90)
+  R($4 -910 90 -690 310)
+  R($5 290 890 510 1110)
+  R($6 -800 820 580 1180)
+  R($6 -980 -420 -620 2420)
+  R($6 -980 2420 -620 3180)
+  R($6 -980 -380 -620 380)
+  R($1 -1050 2325 -525 3275)
+  R($2 -1050 -475 -525 475)
+ )
+ N(3 I(NOUT)
+  R($4 690 2890 910 3110)
+  R($4 690 2490 910 2710)
+  R($4 690 90 910 310)
+  R($4 690 -310 910 -90)
+  Q($6 800 20 * 380 940 * * 1620 620 * * 2420 980 * * 1980 1300 * * 20)
+  R($6 620 2420 980 3180)
+  R($6 620 -380 980 380)
+  R($10 799 1799 801 1801)
+  R($1 525 2325 1050 3275)
+  R($2 525 -475 1050 475)
+ )
+ kk   # invalid
+ N(4
+  R($4 -110 -310 110 -90)
+  R($4 -110 90 110 310)
+  R($4 -110 90 110 310)
+  R($4 -110 -310 110 -90)
+  R($6 -180 -380 180 380)
+  R($6 -180 -380 180 380)
+  R($7 -125 -325 125 -75)
+  R($7 -125 75 125 325)
+  R($8 -1400 -450 1400 450)
+  R($2 -275 -475 275 475)
+ )
+ N(5
+  R($4 -110 2490 110 2710)
+  R($4 -110 2890 110 3110)
+  R($4 -110 2890 110 3110)
+  R($4 -110 2490 110 2710)
+  R($6 -180 2420 180 3180)
+  R($6 -180 2420 180 3180)
+  R($7 -125 2475 125 2725)
+  R($7 -125 2875 125 3125)
+  R($8 -1400 2350 1400 3250)
+  R($1 -275 2325 275 3275)
+ )
+ kk   # invalid
+ P(1 I(IN))
+ P(2)
+ P(3 I(OUT) kk)
+ P(4)
+ P(5)
+ D(1 D$PMOS
+  Y(-400 2800)
+  E(L 0.25)
+  E(W 0.95)
+  E(AS 0.49875)
+  E(AD 0.26125)
+  E(PS 2.95)
+  E(PD 1.5)
+  T(S 2)
+  T(G 1)
+  T(D 5)
+ kk   # invalid
+ )
+ D(2 D$PMOS$1
+  Y(400 2800)
+  E(L 0.25)
+  E(W 0.95)
+  E(AS 0.26125)
+  E(AD 0.49875)
+  E(PS 1.5)
+  E(PD 2.95)
+  T(S 5)
+  T(G 2)
+  T(D 3)
+ )
+ D(3 D$NMOS
+  Y(-400 0)
+  E(L 0.25)
+  E(W 0.95)
+  E(AS 0.49875)
+  E(AD 0.26125)
+  E(PS 2.95)
+  E(PD 1.5)
+  T(S 2)
+  T(G 1)
+  T(D 4)
+ )
+ D(4 D$NMOS$1
+  Y(400 0)
+  E(L 0.25)
+  E(W 0.95)
+  E(AS 0.26125)
+  E(AD 0.49875)
+  E(PS 1.5)
+  E(PD 2.95)
+  T(S 4)
+  T(G 2)
+  T(D 3)
+ )
+)
+X(RINGO
+ N(1 I(FB)
+ kk   # invalid
+  R($4 22850 2490 23070 2710)
+  R($4 22850 2890 23070 3110)
+  R($4 22850 -310 23070 -90)
+  R($4 22850 90 23070 310)
+  R($6 -1700 1620 -1340 1980)
+  R($7 -1645 1675 -1395 1925)
+  R($7 22835 1675 23085 1925)
+  R($8 -1720 1600 23160 2000)
+  R($11 -1 1799 1 1801)
+ )
+ N(2 I(VSS)
+  R($4 2530 -310 2750 -90)
+  R($4 2530 90 2750 310)
+  R($4 2530 90 2750 310)
+  R($4 2530 -310 2750 -90)
+  R($4 -110 -310 110 -90)
+  R($4 -110 90 110 310)
+  R($4 -110 90 110 310)
+  R($4 -110 -310 110 -90)
+  R($4 5170 -310 5390 -90)
+  R($4 5170 90 5390 310)
+  R($4 5170 90 5390 310)
+  R($4 5170 -310 5390 -90)
+  R($4 7810 -310 8030 -90)
+  R($4 7810 90 8030 310)
+  R($4 7810 90 8030 310)
+  R($4 7810 -310 8030 -90)
+  R($4 10450 -310 10670 -90)
+  R($4 10450 90 10670 310)
+  R($4 10450 90 10670 310)
+  R($4 10450 -310 10670 -90)
+  R($4 13090 -310 13310 -90)
+  R($4 13090 90 13310 310)
+  R($4 13090 90 13310 310)
+  R($4 13090 -310 13310 -90)
+  R($4 15730 -310 15950 -90)
+  R($4 15730 90 15950 310)
+  R($4 15730 90 15950 310)
+  R($4 15730 -310 15950 -90)
+  R($4 18370 -310 18590 -90)
+  R($4 18370 90 18590 310)
+  R($4 18370 90 18590 310)
+  R($4 18370 -310 18590 -90)
+  R($4 21010 -310 21230 -90)
+  R($4 21010 90 21230 310)
+  R($4 21010 90 21230 310)
+  R($4 21010 -310 21230 -90)
+  R($4 23650 -310 23870 -90)
+  R($4 23650 90 23870 310)
+  R($4 23650 90 23870 310)
+  R($4 23650 -310 23870 -90)
+  R($6 2460 -380 2820 380)
+  R($6 2460 -380 2820 380)
+  R($6 -180 -380 180 380)
+  R($6 -180 -380 180 380)
+  R($6 5100 -380 5460 380)
+  R($6 5100 -380 5460 380)
+  R($6 7740 -380 8100 380)
+  R($6 7740 -380 8100 380)
+  R($6 10380 -380 10740 380)
+  R($6 10380 -380 10740 380)
+  R($6 13020 -380 13380 380)
+  R($6 13020 -380 13380 380)
+  R($6 15660 -380 16020 380)
+  R($6 15660 -380 16020 380)
+  R($6 18300 -380 18660 380)
+  R($6 18300 -380 18660 380)
+  R($6 20940 -380 21300 380)
+ kk   # invalid
+  R($6 20940 -380 21300 380)
+  R($6 23580 -380 23940 380)
+  R($6 23580 -380 23940 380)
+  R($11 -1 -1 1 1)
+ )
+ N(3 I(VDD)
+  R($4 2530 2490 2750 2710)
+  R($4 2530 2890 2750 3110)
+  R($4 2530 2890 2750 3110)
+  R($4 2530 2490 2750 2710)
+  R($4 -110 2490 110 2710)
+  R($4 -110 2890 110 3110)
+  R($4 -110 2890 110 3110)
+  R($4 -110 2490 110 2710)
+  R($4 5170 2490 5390 2710)
+  R($4 5170 2890 5390 3110)
+  R($4 5170 2890 5390 3110)
+  R($4 5170 2490 5390 2710)
+  R($4 7810 2490 8030 2710)
+  R($4 7810 2890 8030 3110)
+  R($4 7810 2890 8030 3110)
+  R($4 7810 2490 8030 2710)
+  R($4 10450 2490 10670 2710)
+  R($4 10450 2890 10670 3110)
+  R($4 10450 2890 10670 3110)
+  R($4 10450 2490 10670 2710)
+  R($4 13090 2490 13310 2710)
+  R($4 13090 2890 13310 3110)
+  R($4 13090 2890 13310 3110)
+  R($4 13090 2490 13310 2710)
+  R($4 15730 2490 15950 2710)
+  R($4 15730 2890 15950 3110)
+  R($4 15730 2890 15950 3110)
+  R($4 15730 2490 15950 2710)
+  R($4 18370 2490 18590 2710)
+  R($4 18370 2890 18590 3110)
+  R($4 18370 2890 18590 3110)
+  R($4 18370 2490 18590 2710)
+  R($4 21010 2490 21230 2710)
+  R($4 21010 2890 21230 3110)
+  R($4 21010 2890 21230 3110)
+  R($4 21010 2490 21230 2710)
+  R($4 23650 2490 23870 2710)
+  R($4 23650 2890 23870 3110)
+  R($4 23650 2890 23870 3110)
+  R($4 23650 2490 23870 2710)
+  R($6 2460 2420 2820 3180)
+  R($6 2460 2420 2820 3180)
+  R($6 -180 2420 180 3180)
+  R($6 -180 2420 180 3180)
+  R($6 5100 2420 5460 3180)
+  R($6 5100 2420 5460 3180)
+  R($6 7740 2420 8100 3180)
+  R($6 7740 2420 8100 3180)
+  R($6 10380 2420 10740 3180)
+  R($6 10380 2420 10740 3180)
+  R($6 13020 2420 13380 3180)
+  R($6 13020 2420 13380 3180)
+  R($6 15660 2420 16020 3180)
+  R($6 15660 2420 16020 3180)
+  R($6 18300 2420 18660 3180)
+  R($6 18300 2420 18660 3180)
+  R($6 20940 2420 21300 3180)
+  R($6 20940 2420 21300 3180)
+  R($6 23580 2420 23940 3180)
+  R($6 23580 2420 23940 3180)
+  R($11 -1 2799 1 2801)
+ )
+ N(4
+  R($4 690 2890 910 3110)
+  R($4 690 2490 910 2710)
+  R($4 690 90 910 310)
+  R($4 690 -310 910 -90)
+ )
+ N(5
+  R($4 21810 2890 22030 3110)
+  R($4 21810 2490 22030 2710)
+  R($4 21810 90 22030 310)
+  R($4 21810 -310 22030 -90)
+ )
+ N(6
+  R($4 19170 2890 19390 3110)
+  R($4 19170 2490 19390 2710)
+  R($4 19170 90 19390 310)
+  R($4 19170 -310 19390 -90)
+ )
+ N(7
+  R($4 16530 2890 16750 3110)
+  R($4 16530 2490 16750 2710)
+  R($4 16530 90 16750 310)
+  R($4 16530 -310 16750 -90)
+ )
+ N(8
+  R($4 13890 2890 14110 3110)
+  R($4 13890 2490 14110 2710)
+  R($4 13890 90 14110 310)
+  R($4 13890 -310 14110 -90)
+ )
+ N(9
+  R($4 11250 2890 11470 3110)
+  R($4 11250 2490 11470 2710)
+  R($4 11250 90 11470 310)
+  R($4 11250 -310 11470 -90)
+ )
+ N(10
+  R($4 8610 2890 8830 3110)
+  R($4 8610 2490 8830 2710)
+  R($4 8610 90 8830 310)
+  R($4 8610 -310 8830 -90)
+ )
+ N(11
+  R($4 5970 2890 6190 3110)
+  R($4 5970 2490 6190 2710)
+  R($4 5970 90 6190 310)
+  R($4 5970 -310 6190 -90)
+ )
+ N(12
+  R($4 3330 2890 3550 3110)
+  R($4 3330 2490 3550 2710)
+  R($4 3330 90 3550 310)
+  R($4 3330 -310 3550 -90)
+ kk   # invalid
+ )
+ X(1 INV2 Y(23760 0)
+ kk   # invalid
+  P(0 5)
+  P(1 1)
+  P(3 2)
+  P(4 3)
+ kk   # invalid
+ )
+ X(2 INV2 Y(0 0)
+  P(0 1)
+  P(2 4)
+  P(3 2)
+  P(4 3)
+ )
+ X(3 INV2 Y(2640 0)
+  P(0 4)
+  P(2 12)
+  P(3 2)
+  P(4 3)
+ )
+ X(4 INV2 Y(5280 0)
+  P(0 12)
+  P(2 11)
+  P(3 2)
+  P(4 3)
+ )
+ X(5 INV2 Y(7920 0)
+  P(0 11)
+  P(2 10)
+  P(3 2)
+  P(4 3)
+ )
+ X(6 INV2 Y(10560 0)
+  P(0 10)
+  P(2 9)
+  P(3 2)
+  P(4 3)
+ )
+ X(7 INV2 Y(13200 0)
+  P(0 9)
+  P(2 8)
+  P(3 2)
+  P(4 3)
+ )
+ X(8 INV2 Y(15840 0)
+  P(0 8)
+  P(2 7)
+  P(3 2)
+  P(4 3)
+ )
+ X(9 INV2 Y(18480 0)
+  P(0 7)
+  P(2 6)
+  P(3 2)
+  P(4 3)
+ )
+ X(10 INV2 Y(21120 0)
+  P(0 6)
+  P(2 5)
+  P(3 2)
+  P(4 3)
+ )
+)
diff --git a/testdata/algo/l2n_reader_au_5.l2n b/testdata/algo/l2n_reader_au_5.l2n
new file mode 100644
index 000000000..8b514b029
--- /dev/null
+++ b/testdata/algo/l2n_reader_au_5.l2n
@@ -0,0 +1,487 @@
+#%l2n-klayout
+top(RINGO)
+unit(0.001)
+
+# Layer section
+# This section lists the mask layers (drawing or derived) and their connections.
+
+# Mask layers
+layer($3)
+layer($9)
+layer($4)
+layer($5)
+layer($6)
+layer($10)
+layer($7)
+layer($8)
+layer($11)
+layer($1)
+layer($2)
+
+# Mask layer connectivity
+connect($3 $3 $9 $5)
+connect($9 $3)
+connect($4 $4 $6 $1 $2)
+connect($5 $3 $5 $6)
+connect($6 $4 $5 $6 $10 $7)
+connect($10 $6)
+connect($7 $6 $7 $8)
+connect($8 $7 $8 $11)
+connect($11 $8)
+connect($1 $4 $1)
+connect($2 $4 $2)
+
+# Device class section
+class(PMOS ''
+ param(L 1 0)
+ param(W 1 0)
+ param(AS 1 0)
+ param(AD 1 0)
+ param(PS 1 0)
+ param(PD 1 0)
+ terminal(S)
+ terminal(G)
+ terminal(D)
+)
+class(NMOS ''
+ param(L 1 0)
+ param(W 1 0)
+ param(AS 1 0)
+ param(AD 1 0)
+ param(PS 1 0)
+ param(PD 1 0)
+ terminal(S)
+ terminal(G)
+ terminal(D)
+)
+
+# Device abstracts section
+# Device abstracts list the pin shapes of the devices.
+device(D$PMOS PMOS
+ terminal(S
+  rect($1 (-650 -475) (525 950))
+ )
+ terminal(G
+  rect($3 (-125 -475) (250 950))
+ )
+ terminal(D
+  rect($1 (125 -475) (550 950))
+ )
+)
+device(D$PMOS$1 PMOS
+ terminal(S
+  rect($1 (-675 -475) (550 950))
+ )
+ terminal(G
+  rect($3 (-125 -475) (250 950))
+ )
+ terminal(D
+  rect($1 (125 -475) (525 950))
+ )
+)
+device(D$NMOS NMOS
+ terminal(S
+  rect($2 (-650 -475) (525 950))
+ )
+ terminal(G
+  rect($3 (-125 -475) (250 950))
+ )
+ terminal(D
+  rect($2 (125 -475) (550 950))
+ )
+)
+device(D$NMOS$1 NMOS
+ terminal(S
+  rect($2 (-675 -475) (550 950))
+ )
+ terminal(G
+  rect($3 (-125 -475) (250 950))
+ )
+ terminal(D
+  rect($2 (125 -475) (525 950))
+ )
+)
+
+# Circuit section
+# Circuits are the hierarchical building blocks of the netlist.
+circuit(INV2
+
+ # Nets with their geometries
+ net(1 name(NIN)
+  rect($3 (-525 -250) (250 2500))
+  rect($3 (-1425 -630) (1300 360))
+  rect($3 (-125 -2780) (250 1600))
+  rect($3 (-250 1200) (250 1600))
+  rect($9 (-526 -1801) (2 2))
+  rect($5 (-831 -111) (220 220))
+ )
+ net(2
+  rect($3 (275 -250) (250 2500))
+  rect($3 (-305 -1430) (360 360))
+  rect($3 (-305 820) (250 1600))
+  rect($3 (-250 -4400) (250 1600))
+  rect($4 (-1435 1690) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -3420) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($5 (980 580) (220 220))
+  rect($6 (-1310 -290) (1380 360))
+  rect($6 (-1560 -1600) (360 2840))
+  rect($6 (-360 0) (360 760))
+  rect($6 (-360 -3560) (360 760))
+  rect($1 (-430 1945) (525 950))
+  rect($2 (-525 -3750) (525 950))
+ )
+ net(3 name(NOUT)
+  rect($4 (690 2890) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (-220 -2620) (220 220))
+  rect($4 (-220 -620) (220 220))
+  polygon($6 (-110 110) (0 360) (140 0) (0 1240) (-320 0) (0 800) (360 0) (0 -440) (320 0) (0 -1960))
+  rect($6 (-680 2400) (360 760))
+  rect($6 (-360 -3560) (360 760))
+  rect($10 (-181 1419) (2 2))
+  rect($1 (-276 524) (525 950))
+  rect($2 (-525 -3750) (525 950))
+ )
+ net(4
+  rect($4 (-110 -310) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($6 (-290 -290) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($7 (-305 -705) (250 250))
+  rect($7 (-250 150) (250 250))
+  rect($8 (-1525 -775) (2800 900))
+  rect($2 (-1675 -925) (550 950))
+ )
+ net(5
+  rect($4 (-110 2490) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($6 (-290 -290) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($7 (-305 -705) (250 250))
+  rect($7 (-250 150) (250 250))
+  rect($8 (-1525 -775) (2800 900))
+  rect($1 (-1675 -925) (550 950))
+ )
+
+ # Outgoing pins and their connections to nets
+ pin(1 name(IN))
+ pin(2)
+ pin(3 name(OUT))
+ pin(4)
+ pin(5)
+
+ # Devices and their connections
+ device(1 D$PMOS
+  location(-400 2800)
+  param(L 0.25)
+  param(W 0.95)
+  param(AS 0.49875)
+  param(AD 0.26125)
+  param(PS 2.95)
+  param(PD 1.5)
+  terminal(S 2)
+  terminal(G 1)
+  terminal(D 5)
+ )
+ device(2 D$PMOS$1
+  location(400 2800)
+  param(L 0.25)
+  param(W 0.95)
+  param(AS 0.26125)
+  param(AD 0.49875)
+  param(PS 1.5)
+  param(PD 2.95)
+  terminal(S 5)
+  terminal(G 2)
+  terminal(D 3)
+ )
+ device(3 D$NMOS
+  location(-400 0)
+  param(L 0.25)
+  param(W 0.95)
+  param(AS 0.49875)
+  param(AD 0.26125)
+  param(PS 2.95)
+  param(PD 1.5)
+  terminal(S 2)
+  terminal(G 1)
+  terminal(D 4)
+ )
+ device(4 D$NMOS$1
+  location(400 0)
+  param(L 0.25)
+  param(W 0.95)
+  param(AS 0.26125)
+  param(AD 0.49875)
+  param(PS 1.5)
+  param(PD 2.95)
+  terminal(S 4)
+  terminal(G 2)
+  terminal(D 3)
+ )
+
+)
+circuit(RINGO
+
+ # Nets with their geometries
+ net(1 name(FB)
+  rect($4 (22850 2490) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -3420) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($6 (-24770 1310) (360 360))
+  rect($7 (-305 -305) (250 250))
+  rect($7 (24230 -250) (250 250))
+  rect($8 (-24805 -325) (24880 400))
+  rect($11 (-23161 -201) (2 2))
+ )
+ net(2 name(VSS)
+  rect($4 (2530 -310) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (-2860 -220) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (5060 -220) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (2420 -220) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (2420 -220) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (2420 -220) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (2420 -220) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (2420 -220) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (2420 -220) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (2420 -220) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($6 (-21410 -290) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($6 (-3000 -760) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($6 (4920 -760) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($6 (2280 -760) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($6 (2280 -760) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($6 (2280 -760) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($6 (2280 -760) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($6 (2280 -760) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($6 (2280 -760) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($6 (2280 -760) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($11 (-23941 -381) (2 2))
+ )
+ net(3 name(VDD)
+  rect($4 (2530 2490) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (-2860 -220) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (5060 -220) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (2420 -220) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (2420 -220) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (2420 -220) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (2420 -220) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (2420 -220) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (2420 -220) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (2420 -220) (220 220))
+  rect($4 (-220 180) (220 220))
+  rect($4 (-220 -220) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($6 (-21410 -290) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($6 (-3000 -760) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($6 (4920 -760) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($6 (2280 -760) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($6 (2280 -760) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($6 (2280 -760) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($6 (2280 -760) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($6 (2280 -760) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($6 (2280 -760) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($6 (2280 -760) (360 760))
+  rect($6 (-360 -760) (360 760))
+  rect($11 (-23941 -381) (2 2))
+ )
+ net(4
+  rect($4 (690 2890) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (-220 -2620) (220 220))
+  rect($4 (-220 -620) (220 220))
+ )
+ net(5
+  rect($4 (21810 2890) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (-220 -2620) (220 220))
+  rect($4 (-220 -620) (220 220))
+ )
+ net(6
+  rect($4 (19170 2890) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (-220 -2620) (220 220))
+  rect($4 (-220 -620) (220 220))
+ )
+ net(7
+  rect($4 (16530 2890) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (-220 -2620) (220 220))
+  rect($4 (-220 -620) (220 220))
+ )
+ net(8
+  rect($4 (13890 2890) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (-220 -2620) (220 220))
+  rect($4 (-220 -620) (220 220))
+ )
+ net(9
+  rect($4 (11250 2890) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (-220 -2620) (220 220))
+  rect($4 (-220 -620) (220 220))
+ )
+ net(10
+  rect($4 (8610 2890) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (-220 -2620) (220 220))
+  rect($4 (-220 -620) (220 220))
+ )
+ net(11
+  rect($4 (5970 2890) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (-220 -2620) (220 220))
+  rect($4 (-220 -620) (220 220))
+ )
+ net(12
+  rect($4 (3330 2890) (220 220))
+  rect($4 (-220 -620) (220 220))
+  rect($4 (-220 -2620) (220 220))
+  rect($4 (-220 -620) (220 220))
+ )
+
+ # Subcircuits and their connections
+ circuit(1 INV2 location(23760 0)
+  pin(0 5)
+  pin(1 1)
+  pin(3 2)
+  pin(4 3)
+ )
+ circuit(2 INV2 location(0 0)
+  pin(0 1)
+  pin(2 4)
+  pin(3 2)
+  pin(4 3)
+ )
+ circuit(3 INV2 location(2640 0)
+  pin(0 4)
+  pin(2 12)
+  pin(3 2)
+  pin(4 3)
+ )
+ circuit(4 INV2 location(5280 0)
+  pin(0 12)
+  pin(2 11)
+  pin(3 2)
+  pin(4 3)
+ )
+ circuit(5 INV2 location(7920 0)
+  pin(0 11)
+  pin(2 10)
+  pin(3 2)
+  pin(4 3)
+ )
+ circuit(6 INV2 location(10560 0)
+  pin(0 10)
+  pin(2 9)
+  pin(3 2)
+  pin(4 3)
+ )
+ circuit(7 INV2 location(13200 0)
+  pin(0 9)
+  pin(2 8)
+  pin(3 2)
+  pin(4 3)
+ )
+ circuit(8 INV2 location(15840 0)
+  pin(0 8)
+  pin(2 7)
+  pin(3 2)
+  pin(4 3)
+ )
+ circuit(9 INV2 location(18480 0)
+  pin(0 7)
+  pin(2 6)
+  pin(3 2)
+  pin(4 3)
+ )
+ circuit(10 INV2 location(21120 0)
+  pin(0 6)
+  pin(2 5)
+  pin(3 2)
+  pin(4 3)
+ )
+
+)
diff --git a/testdata/algo/lvs_test3.lvsdb b/testdata/algo/lvs_test3.lvsdb
new file mode 100644
index 000000000..d94707f4b
--- /dev/null
+++ b/testdata/algo/lvs_test3.lvsdb
@@ -0,0 +1,687 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(RINGO)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(bulk)
+ layer(nwell '1/0')
+ layer(poly '3/0')
+ layer(poly_lbl '3/1')
+ layer(diff_cont '4/0')
+ layer(poly_cont '5/0')
+ layer(metal1 '6/0')
+ layer(metal1_lbl '6/1')
+ layer(via1 '7/0')
+ layer(metal2 '8/0')
+ layer(metal2_lbl '8/1')
+ layer(ntie)
+ layer(psd)
+ layer(ptie)
+ layer(nsd)
+
+ # Mask layer connectivity
+ connect(nwell nwell ntie)
+ connect(poly poly poly_lbl poly_cont)
+ connect(poly_lbl poly)
+ connect(diff_cont diff_cont metal1 ntie psd ptie nsd)
+ connect(poly_cont poly poly_cont metal1)
+ connect(metal1 diff_cont poly_cont metal1 metal1_lbl via1)
+ connect(metal1_lbl metal1)
+ connect(via1 metal1 via1 metal2)
+ connect(metal2 via1 metal2 metal2_lbl)
+ connect(metal2_lbl metal2)
+ connect(ntie nwell diff_cont ntie)
+ connect(psd diff_cont psd)
+ connect(ptie diff_cont ptie)
+ connect(nsd diff_cont nsd)
+
+ # Global nets and connectivity
+ global(bulk BULK)
+ global(ptie BULK)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(psd (-650 -875) (525 1750))
+  )
+  terminal(G
+   rect(poly (-125 -875) (250 1750))
+  )
+  terminal(D
+   rect(psd (125 -875) (550 1750))
+  )
+  terminal(B
+   rect(nwell (-125 -875) (250 1750))
+  )
+  kk # invalid
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(psd (-675 -875) (550 1750))
+  )
+  terminal(G
+   rect(poly (-125 -875) (250 1750))
+  )
+  terminal(D
+   rect(psd (125 -875) (525 1750))
+  )
+  terminal(B
+   rect(nwell (-125 -875) (250 1750))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(nsd (-650 -875) (525 1750))
+  )
+  terminal(G
+   rect(poly (-125 -875) (250 1750))
+  )
+  terminal(D
+   rect(nsd (125 -875) (550 1750))
+  )
+  terminal(B
+   rect(bulk (-125 -875) (250 1750))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(nsd (-675 -875) (550 1750))
+  )
+  terminal(G
+   rect(poly (-125 -875) (250 1750))
+  )
+  terminal(D
+   rect(nsd (125 -875) (525 1750))
+  )
+  terminal(B
+   rect(bulk (-125 -875) (250 1750))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(INV2
+
+  # Circuit boundary
+  rect((-1700 -2440) (3100 7820))
+
+  # Nets with their geometries
+  kk # invalid
+  net(1
+   rect(nwell (-1400 1800) (2800 3580))
+   rect(diff_cont (-1510 -650) (220 220))
+   rect(ntie (-510 -450) (800 680))
+  )
+  net(2 name(IN)
+   rect(poly (-525 -250) (250 2500))
+   rect(poly (-1425 -630) (2100 360))
+   rect(poly (-125 -2230) (250 2500))
+   rect(poly (-1050 -3850) (250 2400))
+   rect(poly (550 1200) (250 2400))
+   rect(poly (-250 -6000) (250 2400))
+   rect(poly (-1050 1200) (250 2400))
+   rect(poly_lbl (-525 -2600) (0 0))
+   rect(poly_cont (-830 -110) (220 220))
+  )
+  net(3 name(OUT)
+   rect(diff_cont (-910 90) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (1380 3380) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 -3820) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-1820 3380) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(metal1 (1310 -3710) (360 2220))
+   rect(metal1 (-1900 -800) (2220 360))
+   rect(metal1 (-2280 -2400) (360 2840))
+   rect(metal1 (-360 -3600) (360 1560))
+   rect(metal1 (1240 2040) (360 1560))
+   rect(metal1 (-360 -5160) (360 1560))
+   rect(metal1 (-1960 2040) (360 1560))
+   rect(metal1_lbl (1420 -2180) (0 0))
+   rect(psd (-275 525) (525 1750))
+   rect(psd (-2100 -1750) (525 1750))
+   rect(nsd (1050 -5350) (525 1750))
+   rect(nsd (-2100 -1750) (525 1750))
+  )
+  net(4 name(VSS)
+   rect(diff_cont (-110 90) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 980) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(metal1 (-290 -290) (360 1560))
+   rect(metal1 (-360 -1560) (360 1560))
+   rect(via1 (-305 -705) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(via1 (-250 -1450) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(metal2 (-1525 -775) (2800 1700))
+   rect(metal2_lbl (-160 -540) (0 0))
+   rect(nsd (-1515 -1185) (550 1750))
+  )
+  net(5 name(VDD)
+   rect(diff_cont (-110 2490) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 -1420) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(metal1 (-290 -1490) (360 1560))
+   rect(metal1 (-360 -1560) (360 1560))
+   rect(via1 (-305 -1505) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(metal2 (-1525 -1575) (2800 1700))
+   rect(metal2_lbl (-150 -1250) (0 0))
+   rect(psd (-1525 -475) (550 1750))
+  )
+  net(6 name(BULK)
+   rect(diff_cont (-110 -2160) (220 220))
+   rect(ptie (-510 -450) (800 680))
+  )
+  kk # invalid
+
+  # Outgoing pins and their connections to nets
+  pin(1)
+  pin(2 name(IN))
+  pin(3 name(OUT))
+  pin(4 name(VSS))
+  kk(1 jj(17 2.5 "hello")) # invalid
+  pin(5 name(VDD))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   device(D$PMOS$1 location(800 0))
+   connect(0 S S)
+   connect(1 S D)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D S)
+   connect(0 B B)
+   connect(1 B B)
+  kk # invalid
+   location(-400 3200)
+   param(L 0.25)
+   param(W 3.5)
+   param(AS 1.4)
+   param(AD 1.4)
+   param(PS 6.85)
+   param(PD 6.85)
+   terminal(S 3)
+   terminal(G 2)
+   terminal(D 5)
+   terminal(B 1)
+  kk # invalid
+  )
+  device(3 D$NMOS
+   device(D$NMOS$1 location(800 0))
+   connect(0 S S)
+   connect(1 S D)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D S)
+   connect(0 B B)
+   connect(1 B B)
+   location(-400 -400)
+   param(L 0.25)
+   param(W 3.5)
+   param(AS 1.4)
+   param(AD 1.4)
+   param(PS 6.85)
+   param(PD 6.85)
+   terminal(S 3)
+   terminal(G 2)
+   terminal(D 4)
+   terminal(B 6)
+  )
+  kk # invalid
+
+ )
+ circuit(INV2PAIR
+
+  # Circuit boundary
+  rect((0 -1640) (5740 7820))
+
+  # Nets with their geometries
+  kk # invalid
+  net(1 name(BULK))
+  net(2)
+  net(3)
+  net(4)
+  net(5)
+  net(6)
+  net(7)
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(BULK))
+  pin(2)
+  pin(3)
+  pin(4)
+  pin(5)
+  pin(6)
+  pin(7)
+
+  # Subcircuits and their connections
+  circuit(1 INV2 location(1700 800)
+   pin(0 7)
+   pin(1 5)
+   pin(2 4)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+  circuit(2 INV2 location(4340 800)
+   pin(0 7)
+   pin(1 4)
+   pin(2 6)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+
+ )
+ circuit(RINGO
+
+  # Circuit boundary
+  rect((-1720 -2440) (26880 7820))
+
+  # Nets with their geometries
+  kk # invalid
+  net(1 name(FB)
+   rect(metal1 (-1700 1620) (360 360))
+   rect(via1 (-305 -305) (250 250))
+   rect(via1 (23190 -250) (250 250))
+   rect(metal2 (-23765 -325) (23840 400))
+   rect(metal2_lbl (-22120 -200) (0 0))
+  )
+  net(2 name(OSC)
+   rect(via1 (24435 1675) (250 250))
+   rect(metal2 (-325 -325) (400 400))
+   rect(metal2_lbl (-200 -200) (0 0))
+  )
+  net(3 name(VDD)
+   rect(metal1 (-180 3900) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal2_lbl (-23940 -2220) (0 0))
+  )
+  net(4 name(VSS)
+   rect(metal1 (-180 -2220) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal2_lbl (-23940 1100) (0 0))
+  )
+  net(5)
+  net(6)
+  net(7)
+  net(8)
+  net(9)
+  net(10)
+  net(11)
+  net(12)
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(FB))
+  pin(2 name(OSC))
+  pin(3 name(VDD))
+  pin(4 name(VSS))
+
+  # Subcircuits and their connections
+  circuit(1 INV2PAIR location(19420 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 1)
+   pin(4 10)
+   pin(5 2)
+   pin(6 3)
+  )
+  circuit(2 INV2PAIR location(-1700 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 8)
+   pin(4 1)
+   pin(5 9)
+   pin(6 3)
+  )
+  circuit(3 INV2PAIR location(3580 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 7)
+   pin(4 9)
+   pin(5 12)
+   pin(6 3)
+  )
+  circuit(4 INV2PAIR location(8860 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 6)
+   pin(4 12)
+   pin(5 11)
+   pin(6 3)
+  )
+  circuit(5 INV2PAIR location(14140 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 5)
+   pin(4 11)
+   pin(5 10)
+   pin(6 3)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+  kk # invalid
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(INV2
+
+  # Nets
+  kk # invalid
+  net(1 name('1'))
+  net(2 name('2'))
+  net(3 name('3'))
+  net(4 name('4'))
+  net(5 name('5'))
+  net(6 name('6'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('1'))
+  pin(2 name('2'))
+  pin(3 name('3'))
+  pin(4 name('4'))
+  pin(5 name('5'))
+  pin(6 name('6'))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 3.5)
+   param(AS 1.4)
+   param(AD 1.4)
+   param(PS 6.85)
+   param(PD 6.85)
+   terminal(S 3)
+   terminal(G 2)
+   terminal(D 5)
+   terminal(B 1)
+  )
+  device(2 NMOS
+   name($3)
+   param(L 0.25)
+   param(W 3.5)
+   param(AS 1.4)
+   param(AD 1.4)
+   param(PS 6.85)
+   param(PD 6.85)
+   terminal(S 3)
+   terminal(G 2)
+   terminal(D 4)
+   terminal(B 6)
+  )
+
+ )
+ circuit(INV2PAIR
+
+  # Nets
+  net(1 name('1'))
+  net(2 name('2'))
+  net(3 name('3'))
+  net(4 name('4'))
+  net(5 name('5'))
+  net(6 name('6'))
+  net(7 name('7'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('1'))
+  pin(2 name('2'))
+  pin(3 name('3'))
+  pin(4 name('4'))
+  pin(5 name('5'))
+  pin(6 name('6'))
+  pin(7 name('7'))
+
+  # Subcircuits and their connections
+  circuit(1 INV2 name($2)
+   pin(0 7)
+   pin(1 4)
+   pin(2 6)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name('1'))
+  net(2 name('2'))
+  net(3 name('3'))
+  net(4 name('4'))
+  net(5 name('6'))
+  net(6 name('5'))
+  net(7 name('101'))
+  net(8 name('8'))
+  net(9 name('102'))
+  net(10 name('7'))
+  net(11 name('103'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('1'))
+  pin(2 name('2'))
+  pin(3 name('3'))
+  pin(4 name('4'))
+
+  # Subcircuits and their connections
+  circuit(1 INV2PAIR name($1)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 1)
+   pin(4 5)
+   pin(5 2)
+   pin(6 3)
+  )
+  circuit(2 INV2PAIR name($2)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 1)
+   pin(4 1)
+   pin(5 6)
+   pin(6 3)
+  )
+  circuit(3 INV2PAIR name($3)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 7)
+   pin(4 6)
+   pin(5 8)
+   pin(6 3)
+  )
+  circuit(4 INV2PAIR name($4)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 9)
+   pin(4 8)
+   pin(5 10)
+   pin(6 3)
+  )
+  circuit(5 INV2PAIR name($5)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 11)
+   pin(4 10)
+   pin(5 5)
+   pin(6 3)
+  )
+
+ )
+ circuit(INV2PAIRX
+
+  # Nets
+  net(1 name('1'))
+  net(2 name('2'))
+  net(3 name('3'))
+  net(4 name('4'))
+  net(5 name('5'))
+  net(6 name('6'))
+  net(7 name('7'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('1'))
+  pin(2 name('2'))
+  pin(3 name('3'))
+  pin(4 name('4'))
+  pin(5 name('5'))
+  pin(6 name('6'))
+  pin(7 name('7'))
+
+  # Subcircuits and their connections
+  circuit(1 INV2 name($2)
+   pin(0 7)
+   pin(1 4)
+   pin(2 6)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(() INV2PAIRX mismatch
+  kk( jj("hello" W) jj("world!" E) ) # invalid
+  xref(
+  )
+ )
+ circuit(INV2 INV2 match
+  xref(
+  kk # invalid
+   net(1 1 match)
+   net(6 6 match)
+   net(2 2 match)
+   net(3 3 match)
+   net(5 5 match)
+   net(4 4 match)
+   pin(0 0 match)
+   pin(5 5 match)
+   pin(1 1 match)
+   pin(2 2 match)
+   pin(4 4 match)
+   pin(3 3 match)
+   device(3 2 match)
+   device(1 1 match)
+  kk # invalid
+  )
+ )
+ circuit(INV2PAIR INV2PAIR nomatch
+  xref(
+   net(2 2 mismatch)
+   net(3 3 mismatch)
+   net(4 4 mismatch)
+   net(5 5 mismatch)
+   net(6 6 match)
+   net(7 7 mismatch)
+   net(1 1 mismatch)
+   pin(1 1 match)
+   pin(2 2 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(5 5 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   circuit(1 () mismatch)
+   circuit(2 1 match)
+  )
+ )
+ circuit(RINGO RINGO nomatch
+  xref(
+   net(8 () mismatch kk kk kk )
+   net(7 7 match)
+   net(6 9 match)
+   net(5 11 match)
+   net(9 6 match)
+   net(10 5 match)
+   net(11 10 match)
+   net(12 8 match)
+   net(1 1 mismatch)
+   net(2 2 match)
+   net(3 3 match)
+   net(4 4 match)
+   pin(0 0 match)
+   pin(1 1 match kk)
+   pin(2 2 match)
+   pin(3 3 match)
+   circuit(() 2 mismatch kk)
+   circuit(2 () mismatch)
+   circuit(1 1 match)
+   circuit(3 3 match)
+   circuit(4 4 match)
+   circuit(5 5 match)
+  )
+ )
+)
diff --git a/testdata/algo/lvs_test3_au.lvsdb b/testdata/algo/lvs_test3_au.lvsdb
new file mode 100644
index 000000000..fd107f1b9
--- /dev/null
+++ b/testdata/algo/lvs_test3_au.lvsdb
@@ -0,0 +1,673 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(RINGO)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(bulk)
+ layer(nwell '1/0')
+ layer(poly '3/0')
+ layer(poly_lbl '3/1')
+ layer(diff_cont '4/0')
+ layer(poly_cont '5/0')
+ layer(metal1 '6/0')
+ layer(metal1_lbl '6/1')
+ layer(via1 '7/0')
+ layer(metal2 '8/0')
+ layer(metal2_lbl '8/1')
+ layer(ntie)
+ layer(psd)
+ layer(ptie)
+ layer(nsd)
+
+ # Mask layer connectivity
+ connect(nwell nwell ntie)
+ connect(poly poly poly_lbl poly_cont)
+ connect(poly_lbl poly)
+ connect(diff_cont diff_cont metal1 ntie psd ptie nsd)
+ connect(poly_cont poly poly_cont metal1)
+ connect(metal1 diff_cont poly_cont metal1 metal1_lbl via1)
+ connect(metal1_lbl metal1)
+ connect(via1 metal1 via1 metal2)
+ connect(metal2 via1 metal2 metal2_lbl)
+ connect(metal2_lbl metal2)
+ connect(ntie nwell diff_cont ntie)
+ connect(psd diff_cont psd)
+ connect(ptie diff_cont ptie)
+ connect(nsd diff_cont nsd)
+
+ # Global nets and connectivity
+ global(bulk BULK)
+ global(ptie BULK)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(psd (-650 -875) (525 1750))
+  )
+  terminal(G
+   rect(poly (-125 -875) (250 1750))
+  )
+  terminal(D
+   rect(psd (125 -875) (550 1750))
+  )
+  terminal(B
+   rect(nwell (-125 -875) (250 1750))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(psd (-675 -875) (550 1750))
+  )
+  terminal(G
+   rect(poly (-125 -875) (250 1750))
+  )
+  terminal(D
+   rect(psd (125 -875) (525 1750))
+  )
+  terminal(B
+   rect(nwell (-125 -875) (250 1750))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(nsd (-650 -875) (525 1750))
+  )
+  terminal(G
+   rect(poly (-125 -875) (250 1750))
+  )
+  terminal(D
+   rect(nsd (125 -875) (550 1750))
+  )
+  terminal(B
+   rect(bulk (-125 -875) (250 1750))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(nsd (-675 -875) (550 1750))
+  )
+  terminal(G
+   rect(poly (-125 -875) (250 1750))
+  )
+  terminal(D
+   rect(nsd (125 -875) (525 1750))
+  )
+  terminal(B
+   rect(bulk (-125 -875) (250 1750))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(INV2
+
+  # Circuit boundary
+  rect((-1700 -2440) (3100 7820))
+
+  # Nets with their geometries
+  net(1
+   rect(nwell (-1400 1800) (2800 3580))
+   rect(diff_cont (-1510 -650) (220 220))
+   rect(ntie (-510 -450) (800 680))
+  )
+  net(2 name(IN)
+   rect(poly (-525 -250) (250 2500))
+   rect(poly (-1425 -630) (2100 360))
+   rect(poly (-125 -2230) (250 2500))
+   rect(poly (-1050 -3850) (250 2400))
+   rect(poly (550 1200) (250 2400))
+   rect(poly (-250 -6000) (250 2400))
+   rect(poly (-1050 1200) (250 2400))
+   rect(poly_lbl (-525 -2600) (0 0))
+   rect(poly_cont (-830 -110) (220 220))
+  )
+  net(3 name(OUT)
+   rect(diff_cont (-910 90) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (1380 3380) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 -3820) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-1820 3380) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(metal1 (1310 -3710) (360 2220))
+   rect(metal1 (-1900 -800) (2220 360))
+   rect(metal1 (-2280 -2400) (360 2840))
+   rect(metal1 (-360 -3600) (360 1560))
+   rect(metal1 (1240 2040) (360 1560))
+   rect(metal1 (-360 -5160) (360 1560))
+   rect(metal1 (-1960 2040) (360 1560))
+   rect(metal1_lbl (1420 -2180) (0 0))
+   rect(psd (-275 525) (525 1750))
+   rect(psd (-2100 -1750) (525 1750))
+   rect(nsd (1050 -5350) (525 1750))
+   rect(nsd (-2100 -1750) (525 1750))
+  )
+  net(4 name(VSS)
+   rect(diff_cont (-110 90) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 980) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(metal1 (-290 -290) (360 1560))
+   rect(metal1 (-360 -1560) (360 1560))
+   rect(via1 (-305 -705) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(via1 (-250 -1450) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(metal2 (-1525 -775) (2800 1700))
+   rect(metal2_lbl (-160 -540) (0 0))
+   rect(nsd (-1515 -1185) (550 1750))
+  )
+  net(5 name(VDD)
+   rect(diff_cont (-110 2490) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 -1420) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(metal1 (-290 -1490) (360 1560))
+   rect(metal1 (-360 -1560) (360 1560))
+   rect(via1 (-305 -1505) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(metal2 (-1525 -1575) (2800 1700))
+   rect(metal2_lbl (-150 -1250) (0 0))
+   rect(psd (-1525 -475) (550 1750))
+  )
+  net(6 name(BULK)
+   rect(diff_cont (-110 -2160) (220 220))
+   rect(ptie (-510 -450) (800 680))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1)
+  pin(2 name(IN))
+  pin(3 name(OUT))
+  pin(4 name(VSS))
+  pin(5 name(VDD))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   device(D$PMOS$1 location(800 0))
+   connect(0 S S)
+   connect(1 S D)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D S)
+   connect(0 B B)
+   connect(1 B B)
+   location(-400 3200)
+   param(L 0.25)
+   param(W 3.5)
+   param(AS 1.4)
+   param(AD 1.4)
+   param(PS 6.85)
+   param(PD 6.85)
+   terminal(S 3)
+   terminal(G 2)
+   terminal(D 5)
+   terminal(B 1)
+  )
+  device(2 D$NMOS
+   device(D$NMOS$1 location(800 0))
+   connect(0 S S)
+   connect(1 S D)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D S)
+   connect(0 B B)
+   connect(1 B B)
+   location(-400 -400)
+   param(L 0.25)
+   param(W 3.5)
+   param(AS 1.4)
+   param(AD 1.4)
+   param(PS 6.85)
+   param(PD 6.85)
+   terminal(S 3)
+   terminal(G 2)
+   terminal(D 4)
+   terminal(B 6)
+  )
+
+ )
+ circuit(INV2PAIR
+
+  # Circuit boundary
+  rect((0 -1640) (5740 7820))
+
+  # Nets with their geometries
+  net(1 name(BULK))
+  net(2)
+  net(3)
+  net(4)
+  net(5)
+  net(6)
+  net(7)
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(BULK))
+  pin(2)
+  pin(3)
+  pin(4)
+  pin(5)
+  pin(6)
+  pin(7)
+
+  # Subcircuits and their connections
+  circuit(1 INV2 location(1700 800)
+   pin(0 7)
+   pin(1 5)
+   pin(2 4)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+  circuit(2 INV2 location(4340 800)
+   pin(0 7)
+   pin(1 4)
+   pin(2 6)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+
+ )
+ circuit(RINGO
+
+  # Circuit boundary
+  rect((-1720 -2440) (26880 7820))
+
+  # Nets with their geometries
+  net(1 name(FB)
+   rect(metal1 (-1700 1620) (360 360))
+   rect(via1 (-305 -305) (250 250))
+   rect(via1 (23190 -250) (250 250))
+   rect(metal2 (-23765 -325) (23840 400))
+   rect(metal2_lbl (-22120 -200) (0 0))
+  )
+  net(2 name(OSC)
+   rect(via1 (24435 1675) (250 250))
+   rect(metal2 (-325 -325) (400 400))
+   rect(metal2_lbl (-200 -200) (0 0))
+  )
+  net(3 name(VDD)
+   rect(metal1 (-180 3900) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal2_lbl (-23940 -2220) (0 0))
+  )
+  net(4 name(VSS)
+   rect(metal1 (-180 -2220) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal2_lbl (-23940 1100) (0 0))
+  )
+  net(5)
+  net(6)
+  net(7)
+  net(8)
+  net(9)
+  net(10)
+  net(11)
+  net(12)
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(FB))
+  pin(2 name(OSC))
+  pin(3 name(VDD))
+  pin(4 name(VSS))
+
+  # Subcircuits and their connections
+  circuit(1 INV2PAIR location(19420 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 1)
+   pin(4 10)
+   pin(5 2)
+   pin(6 3)
+  )
+  circuit(2 INV2PAIR location(-1700 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 8)
+   pin(4 1)
+   pin(5 9)
+   pin(6 3)
+  )
+  circuit(3 INV2PAIR location(3580 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 7)
+   pin(4 9)
+   pin(5 12)
+   pin(6 3)
+  )
+  circuit(4 INV2PAIR location(8860 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 6)
+   pin(4 12)
+   pin(5 11)
+   pin(6 3)
+  )
+  circuit(5 INV2PAIR location(14140 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 5)
+   pin(4 11)
+   pin(5 10)
+   pin(6 3)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(INV2
+
+  # Nets
+  net(1 name('1'))
+  net(2 name('2'))
+  net(3 name('3'))
+  net(4 name('4'))
+  net(5 name('5'))
+  net(6 name('6'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('1'))
+  pin(2 name('2'))
+  pin(3 name('3'))
+  pin(4 name('4'))
+  pin(5 name('5'))
+  pin(6 name('6'))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 3.5)
+   param(AS 1.4)
+   param(AD 1.4)
+   param(PS 6.85)
+   param(PD 6.85)
+   terminal(S 3)
+   terminal(G 2)
+   terminal(D 5)
+   terminal(B 1)
+  )
+  device(2 NMOS
+   name($3)
+   param(L 0.25)
+   param(W 3.5)
+   param(AS 1.4)
+   param(AD 1.4)
+   param(PS 6.85)
+   param(PD 6.85)
+   terminal(S 3)
+   terminal(G 2)
+   terminal(D 4)
+   terminal(B 6)
+  )
+
+ )
+ circuit(INV2PAIR
+
+  # Nets
+  net(1 name('1'))
+  net(2 name('2'))
+  net(3 name('3'))
+  net(4 name('4'))
+  net(5 name('5'))
+  net(6 name('6'))
+  net(7 name('7'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('1'))
+  pin(2 name('2'))
+  pin(3 name('3'))
+  pin(4 name('4'))
+  pin(5 name('5'))
+  pin(6 name('6'))
+  pin(7 name('7'))
+
+  # Subcircuits and their connections
+  circuit(1 INV2 name($2)
+   pin(0 7)
+   pin(1 4)
+   pin(2 6)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name('1'))
+  net(2 name('2'))
+  net(3 name('3'))
+  net(4 name('4'))
+  net(5 name('6'))
+  net(6 name('5'))
+  net(7 name('101'))
+  net(8 name('8'))
+  net(9 name('102'))
+  net(10 name('7'))
+  net(11 name('103'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('1'))
+  pin(2 name('2'))
+  pin(3 name('3'))
+  pin(4 name('4'))
+
+  # Subcircuits and their connections
+  circuit(1 INV2PAIR name($1)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 1)
+   pin(4 5)
+   pin(5 2)
+   pin(6 3)
+  )
+  circuit(2 INV2PAIR name($2)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 1)
+   pin(4 1)
+   pin(5 6)
+   pin(6 3)
+  )
+  circuit(3 INV2PAIR name($3)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 7)
+   pin(4 6)
+   pin(5 8)
+   pin(6 3)
+  )
+  circuit(4 INV2PAIR name($4)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 9)
+   pin(4 8)
+   pin(5 10)
+   pin(6 3)
+  )
+  circuit(5 INV2PAIR name($5)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 11)
+   pin(4 10)
+   pin(5 5)
+   pin(6 3)
+  )
+
+ )
+ circuit(INV2PAIRX
+
+  # Nets
+  net(1 name('1'))
+  net(2 name('2'))
+  net(3 name('3'))
+  net(4 name('4'))
+  net(5 name('5'))
+  net(6 name('6'))
+  net(7 name('7'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('1'))
+  pin(2 name('2'))
+  pin(3 name('3'))
+  pin(4 name('4'))
+  pin(5 name('5'))
+  pin(6 name('6'))
+  pin(7 name('7'))
+
+  # Subcircuits and their connections
+  circuit(1 INV2 name($2)
+   pin(0 7)
+   pin(1 4)
+   pin(2 6)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(() INV2PAIRX mismatch
+  xref(
+  )
+ )
+ circuit(INV2 INV2 match
+  xref(
+   net(1 1 match)
+   net(6 6 match)
+   net(2 2 match)
+   net(3 3 match)
+   net(5 5 match)
+   net(4 4 match)
+   pin(0 0 match)
+   pin(5 5 match)
+   pin(1 1 match)
+   pin(2 2 match)
+   pin(4 4 match)
+   pin(3 3 match)
+   device(2 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(INV2PAIR INV2PAIR nomatch
+  xref(
+   net(2 2 mismatch)
+   net(3 3 mismatch)
+   net(4 4 mismatch)
+   net(5 5 mismatch)
+   net(6 6 match)
+   net(7 7 mismatch)
+   net(1 1 mismatch)
+   pin(1 1 match)
+   pin(2 2 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(5 5 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   circuit(1 () mismatch)
+   circuit(2 1 match)
+  )
+ )
+ circuit(RINGO RINGO nomatch
+  xref(
+   net(8 () mismatch)
+   net(7 7 match)
+   net(6 9 match)
+   net(5 11 match)
+   net(9 6 match)
+   net(10 5 match)
+   net(11 10 match)
+   net(12 8 match)
+   net(1 1 mismatch)
+   net(2 2 match)
+   net(3 3 match)
+   net(4 4 match)
+   pin(0 0 match)
+   pin(1 1 match)
+   pin(2 2 match)
+   pin(3 3 match)
+   circuit(() 2 mismatch)
+   circuit(2 () mismatch)
+   circuit(1 1 match)
+   circuit(3 3 match)
+   circuit(4 4 match)
+   circuit(5 5 match)
+  )
+ )
+)