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  <title>LVS Connectivity</title>
  <keyword name="LVS"/>
  <keyword name="LVS Connectivity"/>

  <h2-index/>

  <h2>Intra- and inter-layer connections</h2>

  <p>
  The connectivity setup of a LVS script determines how the connections are made.
  Connections are usually made through conductive materials such as Aluminium or Copper.
  The polygons representing such a material form a connection. Connections can be 
  made across multiple polygons - touching polygons form connected islands of 
  conductive material. This "intra-layer" connectivity is implicit: in LVS scripts
  connections are always made between polygons on the same layer.
  </p>

  <p>
  Connections often cross layers. A via for example is a hole in the insulator
  sheet which connects two metal layers. This connection is modelled using
  a "connect" statement (see <a href="/about/drc_ref_global.xml#connect">connect</a>):
  </p>

  <pre>connect(layer1, layer2)</pre>

  <p>
  A connect statement will specify an electrical connection when the polygons from layer1
  and layer2 overlap. layer1 and layer2 are original or derived layers. "connect" statements
  should appear in the script before the netlist is required - i.e. before "compare" 
  or any other netlist-related statement inside the LVS script. The order of the connect
  statements is not relevant. Neigther is the order of the arguments in "connect": 
  connections are always bidirectional.
  </p>

  <p>
  This is an example for a vertical cross section through a 
  simple 3-metal layer stack with the corresponding "connect" statements:
  </p>

  <p>
  <img src="/manual/metal_connections.png"/>
  </p>

  <p>
  Labels can be included in the connectivity too. Typically labels are placed on
  metal layers. If the labels are drawn on the same layer than the metal shapes
  they are automatically included when using "input" to read the layer. If only
  labels shall be read from a layer, use "labels" (see <a href="/about/drc_ref_global.xml#labels">labels</a>).
  </p>

  <p>
  To attach labels to metal layers, simply connect the label and metal layers:
  </p>

  <pre>metal1_labels = labels(10, 0)
metal1        = input(11, 0)
via1          = input(12, 0)
metal2_labels = labels(13, 0)
metal2        = input(14, 0)

connect(metal1, metal1_labels)
connect(metal1, via1)
connect(via1, metal2)
connect(metal2, metal2_labels)</pre>

  <p>
  If labels are connected to metal layers, their text strings will be used to assign 
  net names to the resulting nets. Ideally, one net is labeled with a single text 
  or with texts with the same text string. In this case, the net name will 
  be non-ambiguous. If multiple labels with different strings are present on a net, 
  the net name will be made from a combination of these names.
  </p>

  <h2>Global connections</h2>

  <p>
  KLayout supports implicit connections made across all polygons on 
  a layer, regardless whether they connect or not. A typical case for
  such a connection is the substrate (aka "bulk"). This connection
  represents the (lightly conductive) substrate material. There is no
  polygon representing the wafer. Instead, a layer is defined which 
  makes a global connection with "connect_global" (see <a href="/about/drc_ref_global.xml#connect_global">connect_global</a>):
  </p>

  <pre>connect_global(bulk, "VSS")</pre>

  <p>
  The arguments to "connect_global" is the globally connected layer and the 
  name of the global net to create. The function will make all shapes on "bulk"
  being connected to a single net "VSS". Every circuit will at least have 
  the "VSS" net. In addition, each circuit will be 
  given a pin called "VSS" which propagates this net to parent circuits.
  </p>

  <h2>Implicit connections</h2>

  <p>
  Implicit connections can be useful to supply preliminary connections
  which are supposed to be created higher up in the hierarchy:
  Imagine a circuit which a big power net for example. When the layout
  is made, the power net may not be completely connected yet because the 
  plan is to connect all parts of this power net later when the
  cell is integrated. In this situation, the 
  subcircuit cell itself won't be LVS clean because the power net is a single
  net schematic-wise, but exist as multiple nets layout-wise. This prevents
  bottom-up verification - a very useful technique to achieve LVS clean 
  layouts.
  </p>

  <p>
  To allow verification of such a cell, "implicit connections" can be
  made by giving the net parts the same name through labels and assume
  these parts are connected: 
  for example to specify implicit connections between all parts of a "VDD" net,
  place a label "VDD" on each part and include the following statement
  in the script:
  </p>

  <pre>connect_implicit("VDD")</pre>

  <p>
  "connect_implicit" (see <a href="/about/drc_ref_global.xml#connect_implicit">connect_implicit</a>)
  can be present multiple times to make many of such connections.
  Implicit connections will only be made on the topmost circuit to prevent false verification results. 
  Be careful not to use this option in a final verification of a full design as power net 
  opens may pass unnoticed.
  </p>

  <p>
  You can include labels of a certain class in a "connect_implicit" statement
  using glob-style pattern:
  </p>

  <pre>connect_implicit("VDD*")</pre>

  <p>
  This will connect all nets labelled with "VDD1" for example or those labelled
  with "VDD_5V". However, this statement will only connect "VDD1" with "VDD1",
  <b>not</b> nets with different labels. I.e. it will not connect "VDD1" with "VDD2"
  labels.
  </p>

  <p>
  "connect_implicit" can be present multiple times. Each statement extends the
  choice of labels which will be connected.
  </p>

  <p>
  The standard method "connect_implicit" will only act on top-level cells.
  However, sometimes the construction of certain library cells requires 
  connecting nets inside subcells. For example, memory cells are often made
  in a way that their common rails are exposed on different sides but 
  not connected internally. Formally, those cells need to be described by
  circuits with multiple pins in the schematic. As the cells are only used
  in certain contexts where these rails are connected, it's sufficient to 
  specify a single pin and connect the rails inside the subcells if labelled
  properly. The following statement will connect all nets labelled with "VDD"
  from the "MEMCELL" subcell:
  </p>

  <pre>connect_implicit("MEMCELL", "VDD")</pre>

  <p>
  If MEMCELL is the top cell, the single-argument, unspecific "connect_implicit"
  rule is applied, unless no such rule is given. In other words: the unspecific
  rule has priority for the top cell.
  </p>

  <p>
  The cell argument can be a glob-style pattern. In this case, the rule is
  applied to all matching cells. Again, the "connect_implicit" rule may be 
  given multiple times. In this case, all matching occurances act together.
  </p>

  <p>
  The "connect_implicit" statements must be given before the netlist is 
  extracted. Typically this happens before or shortly after "connect"
  statements.
  </p>

  <h2>Explicit connections</h2>

  <p>
  Explicit connections can be useful to enforce a connection in the layout 
  which is made in the schematic, but not physically on the level of the cell.
  For example consider the following layout for an inverter:
  </p>

  <p>
  <img src="/manual/inv.png"/>
  </p>

  <p>
  In the layout there are no tie-down diodes, hence there is no physical 
  connection to the n-well region and no physical connection to the bulk
  substrate. This saves space, but these diodes need to be added by other 
  ways.
  Usually this is done when the standard cells are combined into 
  macros. Filler cells will be added which include these substrate and
  well contacts.
  </p>

  <p>
  On the inverter level however, there is no such connection. Therefore
  the inverter has separate bulk and n-well pins. The schematic sometimes
  is a simplified version which does not offer these pins. Hence there is
  an intrinsic mismatch between layout and schematic.
  </p>

  <p>
  <img src="/manual/inv_explicit.png"/>
  </p>

  <p>
  To align layout and schematics, bulk and VSS pins can be connected
  explicitly. Same for n-well and VDD.
  There is a certain risk to forget making these connections later. 
  But this risk can be mitigated by implementing DRC rules which
  demand at least one tie-down diode for each isolated n-well island
  or the bulk.
  </p>

  <p>
  To establish an explicit connection, make sure that n-well and 
  bulk have proper names. For the n-well this can be done by creating
  labels on the n-well islands giving them a proper name - e.g. "NWELL".
  The bulk isn't a real layout layer with polygons on it. Using "connect_global"
  will both connect everthing on this layer and give it a name.
  </p>

  <p>
  The following code will connect the bulk net with "VSS" inside the cell "INV":
  </p>

  <pre>connect_global(bulk, "BULK")
...
connect_explicit("INV", [ "BULK", "VSS" ])
</pre>

  <p>
  The cell name can be a pattern. For example "INV*" will apply this rule on all 
  cells starting with "INV".
  The cell is not mandatory: if it is omitted, the rule is applied to top level only
  to avoid introducing rules in subcells where they would mask layout errors.
  </p>

  <p>
  An explicit connection will also imply implicit connections on the nets 
  listed in the net names. So in the example above, different pieces of "VSS"
  are connected even if they are not physically connected.
  </p>

</doc>
