42 lines
1.3 KiB
Verilog
42 lines
1.3 KiB
Verilog
/**********************************************************************
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* $my_pow example -- Verilog HDL test bench.
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*
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* Verilog test bench to test the $my_pow PLI application.
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*
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* For the book, "The Verilog PLI Handbook" by Stuart Sutherland
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* Copyright 1999 & 2001, Kluwer Academic Publishers, Norwell, MA, USA
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* Contact: www.wkap.il
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* Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
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* Contact: www.sutherland-hdl.com
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*********************************************************************/
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`timescale 1ns / 1ns
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module test;
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reg [32:0] result;
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reg a, b;
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buf i1 (c,a);
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initial
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begin
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$display("Start simulation pow_test.v");
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a = 1;
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b = 0;
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/* Test $my_pow with invalid arguments */
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/* These invalid calls will need to be commented out to use */
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/* the valid calls to $my_pow in simulation */
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// #1 result = $my_pow;
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// #1 result = $my_pow();
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// #1 result = $my_pow(1);
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// #1 result = $my_pow(2,i1);
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// #1 result = $my_pow(1,2,3);
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/* Test $my_pow with valid values */
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#1 $display("$my_pow(2,3) returns %d", $my_pow(2,3));
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#1 result = $my_pow(a,b);
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#1 $display("$my_pow(a,b) returns %d (a=%d b=%d)", result, a, b);
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// #1 $stop;
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#1 $finish(0);
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end
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endmodule
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/*********************************************************************/
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