98 lines
2.0 KiB
Verilog
98 lines
2.0 KiB
Verilog
// This module generate M single 2*HW-1 bit vector each T time steps
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module stimulus #(parameter W = 8, M = 200, MAX = 256) (
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input bit clk, reset,
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output reg [W-1:0] x
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);
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int i;
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initial begin
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@(negedge reset);
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for (i = 0; i < M; i=i+1) begin
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@(negedge clk);
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x = {$random} % MAX;
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end
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end
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endmodule
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module test;
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parameter M = 200; // number of test vectors
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parameter W = 8; // bit width of input vecotrs
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parameter T = 10; // for timing
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parameter D = 8; // depth of pipeline, MAX of 8
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parameter K = 10; // distance between boundaries of pipeline
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parameter S = 2*M*T + 12*D;
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parameter MAX = D*K;
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bit clk =0, reset = 0;
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wire [W-1:0] xin;
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wire [W-1:0] din = K;
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wire [W-1:0] dout, bout, xout;
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wire [2:0] lin = 3'b111; // -1 in fact
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wire [2:0] lout;
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int x_gold; // for computing expected result
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initial forever #T clk = ~clk;
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stimulus #(W, M, MAX) stim (.clk(clk), .reset(reset), .x(xin));
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diq_array #(W, D) duv (.clk(clk), .reset(reset),
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.din(din), .bin(8'd0), .xin(xin), .lin(lin),
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.dout(dout), .bout(bout), .xout(xout),
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.lout(lout) );
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initial begin: checking
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@(negedge reset);
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@(posedge clk);
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repeat (D) @(negedge clk);
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forever begin
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@(posedge clk);
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#1;
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// checking dout
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if (dout !== din) begin
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$display("ERROR");
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$finish;
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end
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// checking bout
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if (bout !== MAX) begin
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$display("ERROR");
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$finish;
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end
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// checking lout
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x_gold = xout-1; // dirty fix, for example xin = 30 muste be reported as 2
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if (lout !== x_gold/K) begin
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$display("ERROR");
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$finish;
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end
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end
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end
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initial begin
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doreset();
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#S;
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$display("PASSED");
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$finish;
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end
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task doreset;
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begin
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@(negedge clk);
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reset = 1;
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repeat (5) @(negedge clk);
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reset = 0;
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end
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endtask
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endmodule
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