65 lines
905 B
Verilog
65 lines
905 B
Verilog
module top;
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initial begin: b_label
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$display("PASSED");
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end: b_label
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initial fork:fj_label
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join:fj_label
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initial fork:fja_label
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join_any:fja_label
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initial fork:fjn_label
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join_none:fjn_label
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task t_label;
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endtask: t_label
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task twa_label(input arg);
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endtask: twa_label
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function fn_label;
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input arg;
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endfunction: fn_label
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function fa_label(input in);
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endfunction: fa_label
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endmodule:top
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macromodule extra;
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parameter add_inv = 1;
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reg a;
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wire y, yb;
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pbuf dut(y, a);
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if (add_inv) begin: g_label
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pinv dut2(yb, y);
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end: g_label
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endmodule: extra
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package pkg;
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endpackage: pkg
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program pgm;
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class foo;
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endclass: foo
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endprogram: pgm
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primitive pbuf (out, in);
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output out;
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input in;
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table
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0 : 0;
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1 : 1;
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endtable
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endprimitive: pbuf
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primitive pinv (output out, input in);
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table
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0 : 1;
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1 : 0;
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endtable
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endprimitive: pinv
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