42 lines
717 B
Verilog
42 lines
717 B
Verilog
// Tests that the signedness for struct members is handled correctly
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module test;
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struct packed {
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logic [15:0] x;
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logic signed [15:0] y;
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} s;
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bit failed = 1'b0;
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`define check(x) \
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if (!(x)) begin \
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$display("FAILED: ", `"x`"); \
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failed = 1'b1; \
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end
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initial begin
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s.x = -1;
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s.y = -1;
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`check(!$is_signed(s.x));
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`check($is_signed(s.y));
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// These evaluate as signed
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`check($signed(s.x) < 0);
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`check(s.y < 0);
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// These all evaluate as unsigned
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`check(s.x > 0);
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`check(s.y[15:0] > 0)
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`check({s.y} > 0)
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`check($unsigned(s.y) > 0)
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`check(s.y > 16'h0)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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