28 lines
467 B
Verilog
28 lines
467 B
Verilog
/* PR#704 */
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module foo;
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reg [80*8:1] filename;
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reg [31:0] memory[1:2048];
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initial filename = "ivltests/pr704.hex";
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initial begin
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$display("The filename is %0s", filename);
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$readmemb(filename, memory, 1);
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if (memory[1] !== 32'haa_aa_aa_aa) begin
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$display("FAILED");
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$finish;
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end
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if (memory[2] !== 32'h55_55_55_55) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule
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