66 lines
1.8 KiB
Verilog
66 lines
1.8 KiB
Verilog
module bug;
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reg [7:0] Data[0:3][0:15];
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reg [7:0] Expect0;
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reg [7:0] Expect1;
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reg [7:0] Expect2;
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reg [7:0] Expect3;
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reg [7:0] Actual0;
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reg [7:0] Actual1;
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reg [7:0] Actual2;
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reg [7:0] Actual3;
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integer i;
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integer j;
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reg Failed = 0;
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initial begin
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for (i = 0; i < 4; i = i + 1) begin
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for (j = 0; j < 16; j = j + 1) begin
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Data[i][j] = (i << 4) + j;
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end
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end
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// this catches the original bug
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for (j = 0; j < 16; j = j + 1) begin
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Expect0 = 0*16 + j; Actual0 = Data[0][j];
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Expect1 = 1*16 + j; Actual1 = Data[1][j];
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Expect2 = 2*16 + j; Actual2 = Data[2][j];
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Expect3 = 3*16 + j; Actual3 = Data[3][j];
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$display("%h %h %h %h", Actual0, Actual1, Actual2, Actual3);
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if (Actual0 !== Expect0) Failed = 1;
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if (Actual1 !== Expect1) Failed = 1;
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if (Actual2 !== Expect2) Failed = 1;
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if (Actual3 !== Expect3) Failed = 1;
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end
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// extended tests to check the bug fix doesn't break anything else
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for (i = 0; i < 4; i = i + 1) begin
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Expect0 = i*16 + 0; Actual0 = Data[i][0];
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Expect1 = i*16 + 3; Actual1 = Data[i][3];
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Expect2 = i*16 + 6; Actual2 = Data[i][6];
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Expect3 = i*16 + 9; Actual3 = Data[i][9];
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$display("%h %h %h %h", Actual0, Actual1, Actual2, Actual3);
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if (Actual0 !== Expect0) Failed = 1;
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if (Actual1 !== Expect1) Failed = 1;
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if (Actual2 !== Expect2) Failed = 1;
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if (Actual3 !== Expect3) Failed = 1;
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end
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Expect0 = 0*16 + 0; Actual0 = Data[0][0];
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Expect1 = 0*16 + 9; Actual1 = Data[0][9];
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Expect2 = 3*16 + 0; Actual2 = Data[3][0];
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Expect3 = 3*16 + 9; Actual3 = Data[3][9];
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$display("%h %h %h %h", Actual0, Actual1, Actual2, Actual3);
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if (Actual0 !== Expect0) Failed = 1;
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if (Actual1 !== Expect1) Failed = 1;
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if (Actual2 !== Expect2) Failed = 1;
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if (Actual3 !== Expect3) Failed = 1;
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if (Failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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