82 lines
2.4 KiB
Verilog
82 lines
2.4 KiB
Verilog
/***********************************************************************
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*
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* Copyright (C) 2011 Adrian Wise
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*
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***********************************************************************
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*
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* This is a testbench exercising gate-level modelling of DTL gates,
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* distilled down (as a test-case) from a much larger design.
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* The gates can only pull down strongly to ground and have a weak
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* pull-up.
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*
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* This illustrates a problem in the git master branch as of 24 December
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* 2011, where a gate that does not pull-up strongly cannot drive a bit
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* of a bus (to either logic level), but can drive a single-bit wire
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* correctly.
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*
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* This is an extended version of the test case provided with the
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* bug report, to cover part selects with a non-zero base, and to
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* make the error checking a bit more robust.
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**********************************************************************/
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`timescale 1 ns / 100 ps
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module dtl_inv (op, in1);
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output op;
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input in1;
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not (strong0, pull1) #16 not1 (op, in1);
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endmodule // dtl_inv
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module top;
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reg d;
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wire w;
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wire [1:0] b;
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reg pass;
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dtl_inv u_1 (.op(w), .in1(d));
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dtl_inv u_2 (.op(b[0]), .in1(d));
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dtl_inv u_3 (.op(b[1]), .in1(b[0]));
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initial begin
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pass = 1'b1;
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d = 1'b0;
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# 100;
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if ((w !== 1'b1) || (b[0] !== 1'b1) || (b[1] !== 1'b0)) begin
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$display("Failed (w !== b[0]): d = %b, w = %b, b = %b", d, w, b);
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pass = 1'b0;
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end
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d = 1'b1;
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# 100;
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if ((w !== 1'b0) || (b[0] !== 1'b0) || (b[1] !== 1'b1)) begin
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$display("Failed (w !== b[0]): d = %b, w = %b, b = %b", d, w, b);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule // top
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