36 lines
832 B
Verilog
36 lines
832 B
Verilog
module bug;
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reg [3:0] r1;
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wire [3:0] w1;
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wire [3:0] w2;
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assign w1 = r1;
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assign w2 = w1;
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reg fail = 0;
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initial begin
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r1 = 0;
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#1 $display("%b %b %b", r1, w1, w2);
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if ((r1 !== 4'b0000) || (w1 !== 4'b0000) || (w2 !== 4'b0000)) fail = 1;
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force w1 = 4'bz;
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#1 $display("%b %b %b", r1, w1, w2);
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if ((r1 !== 4'b0000) || (w1 !== 4'bzzzz) || (w2 !== 4'bzzzz)) fail = 1;
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r1 = 1;
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#1 $display("%b %b %b", r1, w1, w2);
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if ((r1 !== 4'b0001) || (w1 !== 4'bzzzz) || (w2 !== 4'bzzzz)) fail = 1;
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release w1;
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#1 $display("%b %b %b", r1, w1, w2);
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if ((r1 !== 4'b0001) || (w1 !== 4'b0001) || (w2 !== 4'b0001)) fail = 1;
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r1 = 2;
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#1 $display("%b %b %b", r1, w1, w2);
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if ((r1 !== 4'b0010) || (w1 !== 4'b0010) || (w2 !== 4'b0010)) fail = 1;
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if (fail)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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