44 lines
512 B
Verilog
44 lines
512 B
Verilog
module pr3064375;
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reg CLK;
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reg RST;
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reg Reg1;
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reg Reg2;
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initial begin
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CLK = 0;
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forever begin
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#5 CLK = 1;
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#5 CLK = 0;
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end
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end
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initial begin
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RST = 1;
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#20;
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RST = 0;
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#101;
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$finish(0);
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end
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always @(posedge CLK or posedge RST) begin
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if (RST)
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Reg1 <= 0;
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else
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Reg1 <= !Reg1;
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end
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always @(negedge CLK or posedge RST) begin
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if (RST)
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Reg2 <= 0;
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else
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Reg2 <= Reg1;
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end
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initial begin
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$monitor("CLK %b RST %b Reg1 %b Reg2 %b", CLK, RST, Reg1, Reg2);
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end
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endmodule
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