25 lines
403 B
Verilog
25 lines
403 B
Verilog
module pr2974294;
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reg [7:0] array[1:0];
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wire [7:0] word;
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reg fail;
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assign word = array[0];
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initial begin
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fail = 0;
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#0 $display("%b", word);
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if (word !== 8'bx) fail = 1;
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#1 $display("%b", word);
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if (word !== 8'bx) fail = 1;
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array[0] = 8'd0;
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#0 $display("%b", word);
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if (word !== 8'd0) fail = 1;
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if (fail)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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