43 lines
461 B
Verilog
43 lines
461 B
Verilog
module Top;
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generate
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genvar i;
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for (i = 0; i < 1; i = i + 1) begin
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Sub1 SubMod1();
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end
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endgenerate
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endmodule
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module Sub1;
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wire [7:0] Value;
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Sub2 SubMod2(Value);
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defparam SubMod2.Width = 8;
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initial begin
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#1;
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$display("Value = %h", Value);
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if (Value === 8'hff)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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module Sub2(Out);
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parameter Width = 4;
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output [Width-1:0] Out;
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assign Out = {Width{1'b1}};
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endmodule
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