114 lines
3.1 KiB
Verilog
114 lines
3.1 KiB
Verilog
/*
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* There are a number of problem that this example uncovers.
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*
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* It appears that the inverter connected to the ctl input of the
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* tranif gate is not getting the signal passed to it. It looks
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* like once the ctl signal is pulled into the island it can not
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* propagate the signal back out. The fix may be in the compiler
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* where we should only use the island port signal for the tranif
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* control instead of any signal that connects to the ctl net.
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*
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* When the ctl signal removes the connection between the two
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* nets they should self resolve. Is appears that when the ctl
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* signal is removed the nets stay at their current value.
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*/
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module top;
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reg pass;
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reg ctl, ctl2, in, in2;
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wire y1, y2, ctlb, y2b;
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assign y1 = in;
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pullup (weak1) (y2);
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tranif0 q1(y1, y2, ctl);
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assign y2 = ctl2 ? in2 : 1'bz;
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not q2(ctlb, ctl);
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not q3(y2b, y2);
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initial begin
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pass = 1'b1;
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// The tran gate is closed and both sides should track 'in'.
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ctl = 1'b0;
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ctl2 = 1'b0;
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in = 1'b1;
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#1;
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if (ctlb !== 1'b1) begin
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$display("Failed ctlb with ctl = 0, expected 1'b1, got %b", ctlb);
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pass = 1'b0;
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end
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if (y2 !== 1'b1) begin
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$display("Failed tran with ctl = 0, in = 1, expected 1'b1, got %b", y2);
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pass = 1'b0;
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end
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if (y2b !== 1'b0) begin
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$display("Failed y2b with ctl = 0, in = 1, expected 1'b0, got %b", y2b);
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pass = 1'b0;
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end
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in = 1'b0;
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#1;
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if (y2 !== 1'b0) begin
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$display("Failed tran with ctl = 0, in = 0, expected 1'b0, got %b", y2);
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pass = 1'b0;
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end
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if (y2b !== 1'b1) begin
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$display("Failed y2b with ctl = 0, in = 0, expected 1'b1, got %b", y2b);
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pass = 1'b0;
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end
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// The tran gate is open so y2 should go high (pullup).
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ctl = 1'b1;
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#1;
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if (ctlb !== 1'b0) begin
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$display("Failed ctlb with ctl = 1, expected 1'b0, got %b", ctlb);
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pass = 1'b0;
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end
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if (y2 !== 1'b1) begin
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$display("Failed tran with ctl = 1, expected 1'b1, got %b", y2);
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pass = 1'b0;
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end
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if (y2b !== 1'b0) begin
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$display("Failed y2b with ctl = 1, expected 1'b0, got %b", y2b);
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pass = 1'b0;
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end
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// Now try driving y2 from in2.
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ctl2 = 1'b1;
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in2 = 1'b1;
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#1;
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if (y2 !== 1'b1) begin
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$display("Failed tran with ctl2 = 1, in2 = 1, expected 1'b1, got %b", y2);
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pass = 1'b0;
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end
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if (y2b !== 1'b0) begin
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$display("Failed y2b with ctl2 = 1, in2 = 1, expected 1'b0, got %b", y2b);
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pass = 1'b0;
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end
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in2 = 1'b0;
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#1;
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if (y2 !== 1'b0) begin
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$display("Failed tran with ctl2 = 1, in2 = 0, expected 1'b0, got %b", y2);
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pass = 1'b0;
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end
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if (y2b !== 1'b1) begin
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$display("Failed y2b with ctl2 = 1, in2 = 0, expected 1'b1, got %b", y2b);
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pass = 1'b0;
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end
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// Now back to just a pullup on y2.
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ctl2 = 1'b0;
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#1;
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if (y2 !== 1'b1) begin
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$display("Failed tran with ctl2 = 0, expected 1'b1, got %b", y2);
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pass = 1'b0;
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end
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if (y2b !== 1'b0) begin
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$display("Failed y2b with ctl2 = 0, expected 1'b0, got %b", y2b);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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