37 lines
823 B
Verilog
37 lines
823 B
Verilog
module top;
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parameter C1 = 1.0e-6;
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reg pass;
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real rval;
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real exp_result;
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initial begin
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pass = 1'b1;
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exp_result = -1000000.0;
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// Check with a constant and a parameter.
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rval = -1 / C1;
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if (rval != exp_result) begin
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$display ("FAILED: -1/%f gave %f, expected %f", C1, rval, exp_result);
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pass = 1'b0;
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end
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// Check with both constants.
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rval = -1 / 1.0e-6;
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if (rval != exp_result) begin
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$display ("FAILED: -1/1.0e-6 gave %f, expected %f", rval, exp_result);
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pass = 1'b0;
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end
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// Check with a positive value.
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exp_result = 1000000.0;
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rval = 1 / C1;
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if (rval != exp_result) begin
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$display ("FAILED: 1/%f gave %f, not expected %f", C1, rval, exp_result);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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