14 lines
396 B
Verilog
14 lines
396 B
Verilog
module top;
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reg[63:0] a;
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initial begin
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a = 64'h7fe8000000000000;
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// This used to fail because we printed floating point using
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// the default buffer which was only 256 bytes long. To fix
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// this the default size was changed to 512 bytes and this is
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// increased when needed (%400.300f, etc.).
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$display("%6.3f", $bitstoreal(a));
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$display("PASSED");
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end
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endmodule
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