This website requires JavaScript.
Explore
Help
Register
Sign In
luke
/
iverilog
mirror of
https://github.com/steveicarus/iverilog.git
Watch
1
Star
0
Fork
You've already forked iverilog
0
Code
Issues
Packages
Projects
Releases
Wiki
Activity
a7c5eceeea
iverilog
/
ivtest
/
ivltests
/
pr2792883.v
10 lines
115 B
Verilog
Raw
Blame
History
module
top
;
parameter
WIDTH
=
dut
.
WIDTH
;
test
dut
(
)
;
endmodule
module
test
;
parameter
WIDTH
=
8
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink