36 lines
729 B
Verilog
36 lines
729 B
Verilog
module bug04_integerDiv;
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reg passed;
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reg signed[31:0] reg0;
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reg signed[31:0] reg1;
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reg signed[31:0] rquot;
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wire signed[31:0] dividend=reg0;
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wire signed[31:0] divisor=reg1;
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wire signed[31:0] quotient;
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assign quotient= dividend/divisor;
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initial begin
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passed = 1'b1;
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reg0=32'h76c3625e;
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reg1=32'hffffffff;
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//BUG here: quotient==32'hxxxxxxxx, should be 32'h893c9da2
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#1 if (quotient !== 32'h893c9da2) begin
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$display("Failed: CA division, expected 32'h893c9da2, got %h",
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quotient);
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passed = 1'b0;
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end
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rquot = reg0/reg1;
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if (rquot !== 32'h893c9da2) begin
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$display("Failed: division, expected 32'h893c9da2, got %h",
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rquot);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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