71 lines
1.5 KiB
Verilog
71 lines
1.5 KiB
Verilog
module top;
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reg pass;
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reg [5:0] cond;
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reg [2:1] expr;
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integer result;
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always @(cond or expr) begin
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casex (cond)
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6'b01_??10 : result = 1;
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{2'b10, 4'b??10} : result = 2;
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{expr, 4'b??01} : result = 3;
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{expr[2], 5'b0??11} : result = 4;
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{expr[2:1], 4'b??11} : result = 5;
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{expr, 4'b??00} : result = 6;
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default : result = 0;
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endcase
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end
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initial begin
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pass = 1'b1;
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cond = 6'b01_xx10;
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#1;
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if (result != 1) begin
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$display("Failed case expr 1 test, got expr %0d", result);
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pass = 1'b0;
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end
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cond = 6'b10_zz10;
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#1;
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if (result != 2) begin
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$display("Failed case expr 2 test, got expr %0d", result);
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pass = 1'b0;
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end
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expr = 2'b1?;
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cond = 6'b1x_xx01;
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#1;
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if (result != 3) begin
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$display("Failed case expr 3 test, got expr %0d", result);
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pass = 1'b0;
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end
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expr = 2'b0z;
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cond = 6'b00_xx11;
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#1;
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if (result != 4) begin
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$display("Failed case expr 4 test, got expr %0d", result);
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pass = 1'b0;
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end
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expr = 2'b?1;
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cond = 6'bx1_xx11;
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#1;
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if (result != 5) begin
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$display("Failed case expr 5 test, got expr %0d", result);
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pass = 1'b0;
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end
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expr = 2'b11;
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cond = 6'b11_xx00;
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#1;
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if (result != 6) begin
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$display("Failed case expr 6 test, got expr %0d", result);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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