24 lines
627 B
Verilog
24 lines
627 B
Verilog
module test (d, en, g, s, a);
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input [31:2] d;
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input en;
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output g, s, a;
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reg g, s, a;
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reg [31:21] r14;
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reg [2:0] r18;
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always @(d or r18 or r14 or en) begin
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casex ({d[31:12],r18[2:0],en})
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{20'b1111_1111_0011_????_????, 3'b???, 1'b1} : s = 1'b1;
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{20'b1111_1111_0010_????_????, 3'b???, 1'b1} : g = 1'b1;
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{{r14[31:21], 9'b0_01??_????}, 3'b???, 1'b?} : a = 1'b1;
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{{r14[31:21], 9'b1_????_????}, 3'b???, 1'b?} : a = 1'b1;
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endcase
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end
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// Other tests check functionality so if this compiles it is fine.
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initial $display("PASSED");
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endmodule
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