29 lines
712 B
Verilog
29 lines
712 B
Verilog
module top;
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reg passed;
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reg [63:0] wide;
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reg [31:0] norm;
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initial begin
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passed = 1'b1;
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if (! $value$plusargs("option=%h", wide)) begin
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$display("FAILED: Unable to read wide option");
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passed = 1'b0;
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end
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if (wide !== 64'h0123456789abcdef) begin
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$display("FAILED: wide expected 64'h0123456789abcdef, got %h", wide);
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passed = 1'b0;
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end
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if (! $value$plusargs("option=%h", norm)) begin
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$display("FAILED: Unable to read normal option");
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passed = 1'b0;
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end
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if (norm !== 32'h89abcdef) begin
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$display("FAILED: normal expected 32'h89abcdef, got %h", norm);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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