22 lines
448 B
Verilog
22 lines
448 B
Verilog
module top;
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reg passed = 1'b1;
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realtime rvar [1:0];
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initial begin
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#1;
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rvar[0] = -1.0;
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if (rvar[0] != -1.0) begin
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$display("Failed: real time array[0], expected -1.0, got %g", rvar[0]);
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passed = 1'b0;
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end
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rvar[1] = 2.0;
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if (rvar[1] != 2.0) begin
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$display("Failed: real time array[1], expected 2.0, got %g", rvar[1]);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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