29 lines
453 B
Verilog
29 lines
453 B
Verilog
// Copyright 2008, Martin Whitaker.
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// This file may be freely copied for any purpose.
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module ternary_add();
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reg Enable;
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reg [7:0] A;
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reg [7:0] B;
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reg C;
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wire [8:0] Y;
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assign Y = Enable ? A + B + C : 0;
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initial begin
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Enable = 1'b1;
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A = 8'd1;
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B = 8'd254;
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C = 1'd1;
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#1 $display("%0d + %0d + %0d = %0d", A, B, C, Y);
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if (Y !== 9'd256) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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