31 lines
453 B
Verilog
31 lines
453 B
Verilog
module t();
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reg [1:0] f;
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reg [1:0] oszok;
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wire [2:0] vosz1;
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genvar i;
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generate
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for(i = 0; i < 4; i = i + 1) begin : reg_tomb_gen
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wire [2:0] vosz1;
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assign vosz1 = i - f + oszok + 1;
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initial begin
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#1;
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if(!i && vosz1 !== 0) begin
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$display("FAIL -- i=%b, f=%b, oszok=%b, vosz1=%b",
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i, f, oszok, vosz1);
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$finish;
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end
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end
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end
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endgenerate
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initial
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begin
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f = 3;
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oszok = 2;
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#2 $display("PASSED");
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end
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endmodule
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