12 lines
325 B
Verilog
12 lines
325 B
Verilog
module top;
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reg signed [7:0] test = -1;
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integer result;
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initial begin
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result = test[7:0]; // A part select is always unsigned (1364-2001 4.5.1)!
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if (result != 32'h0ff) begin
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$display("FAILED part selects are unsigned, got %h, expected 32'h0ff", result);
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end else $display("PASSED");
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end
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endmodule
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