47 lines
781 B
Verilog
47 lines
781 B
Verilog
module top;
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localparam A = 0;
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reg pass = 1'b1;
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generate
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if (A < 1) begin: gen
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task foo_task;
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reg x;
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begin
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x = 1'b0;
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#10;
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x = 1'b1;
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end
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endtask
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end else begin: gen
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task foo_task;
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reg x;
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begin
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x = 1'b1;
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#10;
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x = 1'b0;
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end
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endtask
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end
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endgenerate
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initial begin
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gen.foo_task;
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end
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initial begin
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#9
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if (gen.foo_task.x !== 1'b0) begin
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$display("Failed: expected 1'b0, got %b", gen.foo_task.x);
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pass = 1'b0;
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end
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#2
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if (gen.foo_task.x !== 1'b1) begin
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$display("Failed: expected 1'b1, got %b", gen.foo_task.x);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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