iverilog/ivtest/ivltests/pr1925360.v

10 lines
201 B
Verilog

`define MAC(i) $display(i);
module top;
initial begin
if ("$display(in);" != ``MAC(in))
$display("FAILED: expected \"display(in);\", got \"`MAC(in)\"");
else $display("PASSED");
end
endmodule