41 lines
901 B
Verilog
41 lines
901 B
Verilog
module test;
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reg pass = 1'b1;
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parameter con = 1 * -2;
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parameter a = 1;
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parameter b = -2;
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parameter mul = a * b;
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parameter sum = a + b;
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parameter div = b / a;
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parameter sub = b - a;
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initial begin
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if (con != -2) begin
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$display("FAILED: constant mult. expected -2, got %d (%b)", con, con);
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pass = 1'b0;
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end
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if (mul != -2) begin
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$display("FAILED: multiplication expected -2, got %d (%b)", mul, mul);
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pass = 1'b0;
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end
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if (div != -2) begin
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$display("FAILED: division expected -2, got %d (%b)", div, div);
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pass = 1'b0;
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end
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if (sum != -1) begin
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$display("FAILED: summation expected -1, got %d (%b)", sum, sum);
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pass = 1'b0;
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end
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if (sub != -3) begin
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$display("FAILED: subtraction expected -3, got %d (%b)", sub, sub);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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