36 lines
877 B
Verilog
36 lines
877 B
Verilog
/* This test checks two thing:
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*
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* The first is that the AND arguments are padded if one is
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* smaller than the other. This was causing an assert.
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*
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* The second is that the reduction operator does not pass
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* the expression width to its arguments. This will give an
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* incorrect result (01 vs 00).
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*/
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module test ();
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reg pass = 1'b1;
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reg [1:0] ra;
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wire [1:0] a;
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wire [3:0] b = 4'b1111;
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wire [3:0] c = 4'b1111;
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assign a = |((c & ~(1'b1<<9'h00)) & b);
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initial begin
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#1;
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if (a !== 2'b01) begin
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$display("FAILED: cont. assign, expected 2'b01, got %b", a);
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pass = 1'b0;
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end
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ra = |((c & ~(1'b1<<9'h00)) & b);
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if (ra !== 2'b01) begin
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$display("FAILED: proc. assign, expected 2'b01, got %b", ra);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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