17 lines
304 B
Verilog
17 lines
304 B
Verilog
module top;
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parameter cond = 1;
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parameter value = 25;
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parameter test = (cond) ? 5: 0;
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defparam dut.lwrval = (cond == 1) ? 6: (100/value) + 0.5;
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lower dut();
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endmodule
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module lower;
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parameter lwrval = 4;
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initial if (lwrval != 6.0) $display("FAILED"); else $display("PASSED");
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endmodule
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