47 lines
833 B
Verilog
47 lines
833 B
Verilog
`timescale 1ns/1ns
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module test;
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reg pass = 1;
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reg [3 : 0] A = 4'hf;
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wire [3 : 0] a_lls, a_lrs;
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reg signed [3 : 0] B = 7;
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wire signed [3 : 0] b_als, b_ars;
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assign a_lls = A<<4;
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assign a_lrs = A>>4;
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assign b_als = B<<<4;
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assign b_ars = B>>>4;
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initial begin
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#1;
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if (a_lls !== 4'b0) begin
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$display("FAILED assigning logical left shift");
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pass = 0;
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end
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if (a_lrs !== 4'b0) begin
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$display("FAILED assigning logical right shift");
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pass = 0;
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end
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if (b_als !== 4'b0) begin
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$display("FAILED assigning arithmetic left shift");
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pass = 0;
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end
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if (b_ars !== 4'h0) begin
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$display("FAILED assigning arithmetic right shift (0)");
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pass = 0;
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end
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#1 B = -8;
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#1;
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if (b_ars !== 4'hf) begin
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$display("FAILED assigning arithmetic right shift (1)");
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pass = 0;
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end
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if (pass) $display("PASSED");
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end
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endmodule // test
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