23 lines
462 B
Verilog
23 lines
462 B
Verilog
module top;
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reg pass = 1;
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initial begin
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if (4'sd2 < -2) begin
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$display("Failed for operator <");
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pass = 0;
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end
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if (4'sd2 <= -2) begin
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$display("Failed for operator <=");
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pass = 0;
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end
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if (-2 > 4'sd2) begin
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$display("Failed for operator >");
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pass = 0;
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end
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if (-2 >= 4'sd2) begin
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$display("Failed for operator >=");
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pass = 0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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