40 lines
567 B
Verilog
40 lines
567 B
Verilog
// pr1866215
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module A (CH, CL, SH, SL);
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output [31:0] SL;
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output [31:0] CL;
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output [47:32] SH;
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output [47:32] CH;
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B B0 (CH, CL, SH, SL);
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assign SH = 'hff;
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assign SL = 32'haaaaaaaa;
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assign CH = 'hff;
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assign CL = 32'h55555555;
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endmodule
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module B (CH, CL, SH, SL);
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input [37:32] CH;
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input [31:0] CL;
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input [38:32] SH;
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input [31:0] SL;
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C C0 (CH, CL, SH, SL);
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endmodule
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module C (CH, CL, SH, SL);
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input [38:32] CH;
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input [31:0] CL;
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input [39:32] SH;
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input [31:0] SL;
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initial #1 $display("CH=%h, CL=%h, SH=%h, SL=%h", CH, CL, SH, SL);
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endmodule
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