31 lines
630 B
Verilog
31 lines
630 B
Verilog
// Copyright 2007, Martin Whitaker.
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// This code may be freely copied for any purpose.
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module generate_memory();
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generate
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genvar b;
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for (b = 0; b < 4; b = b + 1) begin: Byte
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reg [7:0] Data[0:3];
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end
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endgenerate
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integer i;
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initial begin
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for (i = 0; i < 4; i = i + 1) begin
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Byte[0].Data[i] = i*16 + 1;
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Byte[1].Data[i] = i*16 + 2;
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Byte[2].Data[i] = i*16 + 3;
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Byte[3].Data[i] = i*16 + 4;
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end
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for (i = 0; i < 4; i = i + 1) begin
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$display("%h", Byte[0].Data[i]);
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$display("%h", Byte[1].Data[i]);
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$display("%h", Byte[2].Data[i]);
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$display("%h", Byte[3].Data[i]);
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end
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end
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endmodule
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