20 lines
482 B
Verilog
20 lines
482 B
Verilog
//
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// The output from the display should be:
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// i is '1'; j is '111'; k is '0'
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//
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module test;
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reg one = 1;
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reg i, k, kr;
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reg [2:0] j, jr;
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initial
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begin
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i = ($signed(3'b111) === 3'b111);
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j = $signed(3'b110) >>> 1;
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jr = $signed(3'b110) >>> one;
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k = (($signed(3'b110) >>> 1) === 3'b111);
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kr = (($signed(3'b110) >>> one) === 3'b111);
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$display("i is '%b'; j is '%b'; k is '%b'", i, j, k);
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$display("runtime ; j is '%b'; k is '%b'", jr, kr);
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end
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endmodule
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