46 lines
1.2 KiB
Verilog
46 lines
1.2 KiB
Verilog
module top;
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reg [8*80-1:0] str;
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integer fd, pos, result;
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initial begin
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fd = $fopen("ivltests/pr1819452.txt","rb");
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result = $fgets(str, fd);
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while (!$feof(fd)) begin
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pos = $ftell(fd);
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$display("Found: %5s currently at byte %0d", str[8*10-1:8], pos);
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result = $fgets(str, fd);
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end
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result = $rewind(fd);
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result = $fgets(str, fd);
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pos = $ftell(fd);
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$display("Found: %5s currently at byte %0d", str[8*10-1:8], pos);
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result = $fseek(fd, 0, 0);
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result = $fgets(str, fd);
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pos = $ftell(fd);
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$display("Found: %5s currently at byte %0d", str[8*10-1:8], pos);
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result = $fseek(fd, -3, 2);
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result = $fgets(str, fd);
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pos = $ftell(fd);
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$display("Found: %5s currently at byte %0d", str[8*10-1:8], pos);
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result = $fseek(fd, -6, 1);
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result = $fgets(str, fd);
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pos = $ftell(fd);
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$display("Found: %5s currently at byte %0d", str[8*10-1:8], pos);
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result = $fseek(32'hffffffff, 0, 0);
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$display("Check fseek EOF = %0d", result);
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result = $ftell(32'hffffffff);
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$display("Check ftell EOF = %0d", result);
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result = $rewind(32'hffffffff);
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$display("Check rewind EOF = %0d", result);
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$fclose(fd);
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end
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endmodule
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