46 lines
660 B
Verilog
46 lines
660 B
Verilog
module test;
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reg clock;
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initial begin
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clock = 0;
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forever #5 clock = !clock;
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end
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wire [0:31] read_data1 [0:7];
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reg [0:31] read_data2 [0:7];
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assign read_data1[0] = 0;
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assign read_data1[1] = 1;
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assign read_data1[2] = 2;
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assign read_data1[3] = 3;
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assign read_data1[4] = 4;
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assign read_data1[5] = 5;
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assign read_data1[6] = 6;
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assign read_data1[7] = 7;
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always @(posedge clock) begin: we
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reg [3:0] x;
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for (x=0; x<8; x=x+1) begin
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read_data2[x[2:0]] <= read_data1[x[2:0]];
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end
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end
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always @(posedge clock) begin: wg
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integer i;
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#1 for (i=0; i<8; i=i+1) begin
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$write("%x ", read_data2[i]);
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end
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$display;
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end
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initial begin
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#20;
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$finish(0);
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end
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endmodule // test
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