24 lines
410 B
Verilog
24 lines
410 B
Verilog
module test;
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reg [63:0] i, j;
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initial
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main;
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task main;
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integer k, l, m, n;
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begin
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i = 64'hffff_ffff_ffff_ffff;
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j = 64'hffff_ffff_ffff_ffff;
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k = $signed(i) < $signed(j);
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l = $signed(i) <= $signed(j);
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m = $signed(i) > $signed(j);
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n = $signed(i) >= $signed(j);
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$display("< : %s", k? "Y":"N");
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$display("<=: %s", l? "Y":"N");
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$display("> : %s", m? "Y":"N");
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$display(">=: %s", n? "Y":"N");
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end
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endtask
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endmodule
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