20 lines
310 B
Verilog
20 lines
310 B
Verilog
// Copyright 2007, Martin Whitaker.
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// This code may be freely copied for any purpose.
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module display_index_test();
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reg [2:0] A[1:4];
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integer i;
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initial begin
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for (i = 1; i <= 4; i = i + 1) begin
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A[i] = i;
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end
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for (i = 1; i <= 4; i = i + 1) begin
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$display("%d", A[i]);
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end
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end
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endmodule
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