25 lines
372 B
Verilog
25 lines
372 B
Verilog
module test();
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reg [0:(8*6)-1] identstr= "PASSED";
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reg [7:0] identdata= 8'b0;
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integer i;
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initial
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begin
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// $dumpfile("indexed_part.vcd");
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// $dumpvars;
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end
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initial
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begin
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for (i=0; i<6; i=i+1)
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begin
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#10 identdata = identstr[i*8 +:8];
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$write("%c", identdata);
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end
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$write("\n");
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$finish;
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end
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endmodule // test
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