15 lines
340 B
Verilog
15 lines
340 B
Verilog
module top;
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real rval;
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reg [7:0] rgval;
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initial begin
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rgval = 8'ha5;
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rval = 1234567890;
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$display("Checking h and H: %h, %H", rgval, rgval);
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$display("Checking x and X: %x, %X", rgval, rgval);
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$display("Checking g and G: %g, %G", rval, rval);
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$display("Checking e and E: %e, %E", rval, rval);
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end
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endmodule
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