17 lines
317 B
Verilog
17 lines
317 B
Verilog
`define FAIL
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module top;
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reg[7:0] pattern;
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initial begin
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// Mask off the MSB and the two lower bits.
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pattern = ~0 ^ 2'b11;
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pattern[7] = 0;
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`ifndef FAIL
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#0;
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`endif
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if ((8'b01111110&pattern) == (8'b11111101&pattern)) $display("PASSED");
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else $display("Fail: %b", pattern);
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end
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endmodule
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