54 lines
959 B
Verilog
54 lines
959 B
Verilog
/* PR1637208 */
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module main;
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reg clock;
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reg [31:0] pixel0;
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reg [31:0] mem [0:1];
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always @(posedge clock) begin
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mem[0] <= pixel0;
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end
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always @(posedge clock) begin
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mem[1] <= mem[0];
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end
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reg sel;
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wire [31:0] foo = sel? mem[1] : mem[0];
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initial begin
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clock = 1;
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sel = 0;
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#1 pixel0 = 'h55555555;
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#1 clock = 0;
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#1 clock = 1;
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#1 pixel0 = 'haaaaaaaa;
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#1 clock = 0;
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#1 clock = 1;
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#1 if (mem[0] !== 32'haaaaaaaa) begin
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$display("FAILED -- mem[0] = %h", mem[0]);
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$finish;
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end
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if (mem[1] !== 32'h55555555) begin
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$display("FAILED == mem[1] = %h", mem[1]);
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$finish;
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end
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if (foo !== mem[0]) begin
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$display("FAILED -- mem[sel=0] != %h", foo);
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$finish;
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end
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sel = 1;
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#1 if (foo !== mem[1]) begin
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$display("FAILED -- mem[sel=1] != %h", foo);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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