33 lines
401 B
Verilog
33 lines
401 B
Verilog
//
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// Test the specify block (pr1587634)
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//
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`timescale 1 ns / 1 ps
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/*
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module top();
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reg in;
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initial begin
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in = 0;
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#10 in = 1;
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end
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inv1 g1 (out, in);
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endmodule
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*/
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module inv1 (z, a);
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output z;
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input a;
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not g1(z, a);
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specify
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specparam tpd_a_z_lh = 0.400;
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specparam tpd_a_z_hl = 0.300:0.400:0.500;
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(a -=> z) = (tpd_a_z_lh, tpd_a_z_hl);
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endspecify
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endmodule
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