24 lines
659 B
Verilog
24 lines
659 B
Verilog
module kk_timing (A, B, C, D, E, F);
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input A, B, D, E, F;
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output C;
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wire A, B, D, E, F;
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reg C;
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wire [1:0] BL;
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wire [1:0] BL_X;
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assign BL[0] = E;
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assign BL_X[0] = F;
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wire BL_0 = BL[0] ;
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wire BL_X_0 = BL_X[0];
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specify
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$setuphold(posedge A &&& B, BL[0], 0, 0, C,,,D, BL_X[0]); // line 14 compile fail iverilog_20060618
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$setuphold(posedge A &&& B, BL_0 , 0, 0, C,,,D, BL_X[0]); // line 15 compile fail iverilog_20060618
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$setuphold(posedge A &&& B, BL[0], 0, 0, C,,,D, BL_X_0 ); // line 16 compile pass iverilog_20060618
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$setuphold(posedge A &&& B, BL_0 , 0, 0, C,,,D, BL_X_0 ); // line 17 compile pass iverilog_20060618
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endspecify
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endmodule
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