28 lines
364 B
Verilog
28 lines
364 B
Verilog
module extension_bug();
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reg x;
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reg [3:0] a, b;
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initial begin
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x = 1'b1;
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a = ~1'b1;
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b = ~x;
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$display("a = %b", a);
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if (a !== 4'b1110) begin
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$display("FAILED");
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$finish;
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end
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$display("b = %b", b);
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if (b !== 4'b1110) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule
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