42 lines
706 B
Verilog
42 lines
706 B
Verilog
module main;
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reg b, a;
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initial begin
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b = 0;
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a = 1;
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#1 if (b !== 0) begin
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$display("FAILED -- b starts out as %b", b);
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$finish;
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end
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force b = a;
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#1 if (b !== 1) begin
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$display("FAILED -- b=%b, a=%b", b, a);
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$finish;
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end
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a = 0;
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#1 if (b !== 0) begin
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$display("FAILED -- b=%b, a=%b", b, a);
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$finish;
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end
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a = 1;
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#1 release b;
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#1 a = 0;
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#1 if (b !== 1) begin
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$display("FAILED -- b=%b didnot hold value after release", b);
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$finish;
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end
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b = 0;
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if (b !== 0) begin
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$display("FAILED -- assign failed b=%b", b);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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