34 lines
704 B
Verilog
34 lines
704 B
Verilog
`begin_keywords "1364-2005"
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module test();
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reg [15:0] a;
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reg [7:0] b;
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reg [31:0] expect;
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wire [31:0] actual;
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reg [127:0] long_x;
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real real_x;
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assign actual = a ** b;
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initial begin
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for (a = 0; a < 65535; a = a + 1) begin:outer_loop
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long_x = 1;
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for (b = 0; b < 127; b = b + 1) begin:inner_loop
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real_x = $itor(a) ** $itor(b);
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if (real_x >= 2.0**128.0) disable outer_loop;
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expect = long_x;
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#0; // wait for net propagation
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if (actual !== expect) begin
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$display("FAILED : %0d ** %0d = %0d not %0d", a, b, expect, actual);
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$finish;
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end
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long_x = long_x * a;
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end
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end
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$display("PASSED");
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end
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endmodule
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`end_keywords
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